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Displaying 201-300/499

DVB-C Modulator J.83 Annex A/C
Features
DVB-CSA cores
Features
DVB-S Modulator
Features
DVB-S Modulator Core
Features
DVB-T/H Modulator
Features
DVB-T/H Modulator Core
Features
DXAUI PHY
Features
e1t1 Mapper/Framer
Features
EAVB IP Suite
ECC Core
Features
EFEC20
EFEC7
eMMC 5.0 Firmware Driver
Features
EPCS Serial Flash Controller Core
ES1020 - ARC4 Core
Features
Ethernet 1000BASE-X PCS/PMA
Features
Ethernet VIP
Features
E³ (E-Cube) Series SRAM Compiler
Features
Fast AES
Features
FE80A_E_GENERIC_CORE
Features
FE90A_E_GENERIC_CORE
Features
FE90A_S_GENERIC_CORE
Features
FEA0A_E Core
Features
FEB0G_E Core
Features
FEC0G_E_GENERIC_CORE
Features
FEC0H_E
Features
FEC0L_E_GENERIC_CORE
Features
FFT/IFFT
FHG_DRM Base Band IP
Features
FHG_DRM Base Band IP
Features
FIR Compiler
FIR Compiler II
FireGate - 1394B PHY Layer IP Core
Features
Floating Point Exponential (e^a)
DWFC_piped_fp_add
Features
Floating Point Megafunctions
FR8052
Features
FSA0A_C_T33_Generic_EF_IO
Features
FTDDRII020S
Features
FTIIC010
Features
FXREG050H80F
Features
G.709 RS(255,239) GFEC
G.975 I.4 BCH/RS EFEC
G.975 I.7 BCH/BCH EFEC
G.975 I.9 BCH/BCH EFEC
G13LPDG_LDWPD_01---GSMC 0.13μm 1.5V/12V Light Detect with Photodiode
Features
G13LPDG_PLL_01---GSMC 0.13um 1.5v APLL
Features
G13LPDG_POR_01---GSMC 0.13um Low Power e-Flash 1.5V POR
Features
G13LPDG_PRG_01---GSMC 0.13μm 5v-3.3v&1.5v Power Regulator
Features
G13LPDG_VDT_01---The present IP is a VCC Detector (VDT) circuit. It detects the voltage level of I/O (VIN).
Features
G13V33LPDG_USB11_02---crystalless USB1.1 PHY
Features
G2 AES Core - Altera Edition
AES-G2
Features
G2 AES Core - Platinum Edition
AES-G2
Features
G2 AES Core - Xilinx Edition
AES-G2
Features
GF13V33_DCDCBK_04---GLOBALFOUNDRIES 0.13um 3.3V-1.2V 200mA Synchronous Buck DC-DC
Features
GF13V33_DCDCBK_04B---GLOBALFOUNDRIES 0.11um 3.3V-1.2V 200mA Synchronous Buck DC-DC
Features
GF13V33_POR_01---GLOBALFOUNDRIES 0.13um 1.2V POR
Features
GF13V33_POR_01B---GLOBALFOUNDRIES 0.11um 1.2V POR
Features
GF40LPV25_ADC_08---GF40nm 12-bit 1M/200K Single/Differential 2.5v Rail to Rail SAR ADC
Features
GFP-F Processor IP Core (GFPF-GbE)
Features
GFP-T Processor IP Core (GFPT)
Features
GigE for Machine Vision (GigEVCore1.0)
GigEVCore1.0
Features
GRFPU
Features
GRSPW
GSMC18_MULTIO_02---GSMC 0.18um 1.8V/3.3V Multiple I/O
Features
GSMC18_MULTIO_03---GSMC 0.18um 1.8V/3.3V Multiple I/O
Features
GSMC18_MULTIO_05
Features
GSMC18_POR_03---GSMC 0.18um Power-On Reset
Features
H.264 Video Over IP – HD Encoder Subsystem
H264OIP-HDE
Features
HDMI v1.4 Transmitter IP Core
Features
High performance PCIe-AXI Bridge and/or high channel count DMA
Expresso DMA Bridge Core
Features
High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for TSMC 28HP
dwc_duet_embedded memories_logic libraries_tsmc 28hp
Features
High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for TSMC 28HPM
dwc_duet_embedded memories_logic libraries_tsmc 28hpm
Features
Hs-Mode I2C Controller
Features
I65GV25_ADC_08---IBM 65nm 12-bit 1M/200K Single/Differential 2.5v Rail to Rail SAR ADC
Features
I65LPEV25_ADC_08---IBM 65nm 12Bit 1M/200K Single/Differential 2.5v Rail to Rail SAR ADC
Features
IEEE 802.15.3c (60 GHz PHY) Multi-Gbit/s LDPC Decoder
Features
IEEE 802.1ae MACSEC IP Core for 10 Gbit Ethernet
MACSEC-10G
Features
In-System Sources & Probes
IndigoVision's Control Center
Features
iniCPU, a 8-bit microprocessor
Features
iniG704-E1
Features
iniG704-E1
Features
INT 1020 Giga-bit Multi-port Switch
Features
Int-11500
Features
Integrated PCI Core
Features
Interlaken VIP
Features
Interlaken, 100G for 28nm devices
Interlaken, 100G, 12 Lanes
Interlaken, 100G, 20 Lanes
Interlaken, 150G, 24 Lanes
Interlaken, 40G, 8 Lanes
Interlaken, 50G for 28nm devices
Interleaver / De-interleaver
Features
IP Compiler for PCI Express (Hard IP)
Features
IP Compiler for PCI Express x1 (Soft IP)
Features
IP Compiler for PCI Express x4 (Soft IP)
Features
IP Compiler for PCI Express x8 (Soft IP)
Features
IP Core implements the error-correcting coding I.6 LDPC super FEC code code for the ITU-T G.795.1 recommendation
I.6 LDPC Codec
IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-DX7, LPDDR4 emulation MultiPHY, AXI tunnel to ARC SDP
dwipk_umctl2_elpddr4phy_arc
Features
IP Prototyping Kit for DWC Ethernet QoS Controller on HAPS-DX7, Xilinx GTH PHY, PCIe Connection for PC
dwipk_ethrntqos_xlnxphy_pcie
Features
Displaying 201-300/499
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers



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