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Displaying 1-20/20

AES encryption with selectable data path width for Altera FPGAs
AES-G3
Features
AES encryption with selectable data path width for Xilinx FPGAs
AES-G3
Features
AES G3 Reference Design for Xilinx Processors
Features
AES GCM 100G for OTN Core
AES-GCM-100G-OTN
Features
AES Random Number Generator Core
AES-RNG
Features
AES-CCM core
AES-CCM core
Features
AES-GCM Core
AES-GCM 1G
Features
AES-GCM encryption core for 10G throughput
AES-GCM-10G
Features
AES-GCM encryption for 40G throughput
AES-GCM-40G
Features
AES-XTS Core for Data Storage
AES-XTS
Features
Duplex AES GCM 10G for OTN Core
The DUPLEX-AES-GCM-10G-FOR-OTN
Features
G2 AES Core - Altera Edition
AES-G2
Features
G2 AES Core - Microsemi (was Actel) Edition
AES G2
Features
G2 AES Core - Platinum Edition
AES-G2
Features
G2 AES Core - Xilinx Edition
AES-G2
Features
IEEE 802.1ae MACSEC IP Core for 10 Gbit Ethernet
MACSEC-10G
Features
IPSEC (RFC 4303) 1Gbit IP Core
IPSEC-1G
Features
Multiple SecY IEEE 802.1ae MACsec IP Core for 1Gbit Ethernet
MACSEC-1G
Features
Multiple SecY IEEE 802.1ae MACsec IP Core for 40Gbit Ethernet
MACSEC-40G
Features
Pipelined AES G3 for Video
AES-Video
Features
Displaying 1-20/20
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL



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