According to Cadence, the complaint is based in part on a ruling in June 2000 by the United States District Court for the Northern District of California which dismissed a patent infringement lawsuit filed against Quickturn by Meta, Mentor and Aptix. The dismissal was based on a set of findings that Aptix and its CEO had engaged in a shameful pattern of fraud, including the creation and attempted concealment of fabricated evidence, intended to deceive Quickturn and the District Court. The U.S. Court of Appeals affirmed the District Court's June 2000 ruling in November 2001.
In prepared remarks, Penny Herscher, Cadence executive vice president and chief marketing officer said that the court rulings, “support our long-standing contention that Aptix, with the active support of Mentor and Meta, engaged in outright fraud in the patent infringement complaint against Quickturn. This fraud is the basis for our current complaint. With this lawsuit we are serving notice -- we will not tolerate this sort of malicious prosecution or attempts by competitors to unlawfully abuse the legal system to distract us from our priority, the delivery of leading-edge technologies and second-to-none customer service and support.”
Further, “The facts of the case are clear -- the defendants named in our complaint conspired to fabricate evidence and claim intellectual property that is rightfully ours. We cannot allow this type of fraudulent activity to go unchallenged. We will protect our intellectual property, and we look forward to prevailing in court.”
Expectedly, Mentor president Gregory K. Hinckley said in response to the suit, that while the company had not yet received a copy of the complaint, they believe the claims against Mentor are old news, dating prior to June 2000, and have been twice rejected by the courts.
Also, he said that they are, “disappointed that Cadence would choose to disparage us by re-asserting previously rejected claims. Judge William Alsup of the Northern District Court of California (Docket # C98-00762 WHR (EDL)) ruled in June 2000 that there was no evidence of any Mentor wrongdoing. This ruling was then upheld on appeal in 2001. We would expect that based on these existing rulings this case shall be dismissed,” Hinckley said.
In other legal wrangling, Mentor reported that it won a third summary judgment of patent infringement, the latest for its patent #5,754,827, against Cadence's Quickturn Mercury and Mercury-Plus product lines.
The Court also rejected a motion of patent invalidity by Cadence on this patent. These rulings come in Mentor's patent infringement and theft of trade secrets case against Cadence, which is scheduled for trial on January 6, 2003.
New Products
Dynalith's new PCI card product, iPROVE enables FPGA users and IP designers to verify their designs in a much more efficient and versatile way than conventional FPGA-based verification schemes, the company reported. iPROVE uses 66MHz/64bit DMA-enabled PCI interfacing for higher hardware performance and provides C-interface and HDL-interfacing in the form of API for testing and HW/SW co-simulation. The product also has a Built-In Logic Analyzer and Data Pumping Port to monitor various signals and to send and receive data through external connections, respectively. iPROVE supports SystemC, SCE-MI and TestBuilder. For floating-point multiplier and IDCT cases, iPROVE provides software simulation that is 1000 to2000 times faster than pure software simulation, the company asserted. Dynalith's partnership with Xilinx, Inc. allows the product to support Xilinx devices up to the Virtex II XC2V6000 and will support the Xilinx Virtex II Pro family soon, Dynalith reported.
Also from Xilinx, the company is giving early access of a new technology designed for both hardware and software engineers involved in the common design of programmable systems using Xilinx FPGAs with MicroBlaze and PowerPC processor cores. The new technology expands the company's current solution for programmable systems by enabling customers to define an entire system in ANSI-C to obtain the most optimal implementation by rapidly partitioning and repartitioning between hardware and software, Xilinx said.
In related news, Xilinx also announced its Embedded Development Kit – a design environment for embedded system development using Xilinx embedded processors, which also provide foundational technology for its new co-design capability.
The technology provides a complete set of tools for designing, debugging and optimizing complex systems that use resources such as processors, RAM, DSP functions, high-speed I/O technology, and high density FPGA logic. The co-design tools are unique in the system design tool world with a library of hardware and software components, called Processing Elements (PE) optimized for particular functions. This capability enables the customer to use a best-in-class and domain-specific tool to create an optimized PE. A re-partition is a compile time switch, which enables one to profile, convert to a hardware/software implementation and debug in a matter of minutes rather than days or weeks. The hardware and software PEs come from a variety of sources, including Xilinx and third-party AllianceEDA, AllianceCORE, and Embedded Tools partners.
The announced co-design technology enables a true software-centric design paradigm as the technology re-uses proven hardware implementations in an ANSI-C based design flow. This opens up the capability of using the whole processing potential of the FPGA with embedded processor cores to the software design community.
SynTest Technologies, Inc. announced that its TurboFault fault simulator now has a link to the market-leading Debussy Knowledge-based Debug System from Novas Software, Inc.
Altium Limited announced P-CAD 2002, a new version of its P-CAD PCB design system for layout specialists, contains has over sixty new and enhanced features. Interface elements were redesigned in P-CAD 2002 to give PCB layout specialists enhanced ease of use and a more productive design environment, the company explained. New to the tool is the Design Manager feature that allows users to view and manage design data more easily. It presents spreadsheet-like component and net views that are integrated into the PCB layout environment, allowing superior control over key elements of the design. Another new feature is the Visual Placement Area interactive rules-based placement tool that, when a component is being placed, analyses design constraints and displays overlays representing the legal regions of the board in which a component may be placed. This feature makes the critical component placement phase of PCB design faster and gives more control to the designer.
P-CAD 2002 also allows for the trace of an individual net, connections and objects in their own unique colors so designers can easily see individual nets in the context of the board.
Other new features of P-CAD 2002 include support for Valor's ODB++ file format, support for True Type fonts in Gerber and ODB++, component clearance rule checking, and a number of usability-targeted GUI refinements.
People News
Sequence Design appointed Alan Lipinski to senior vice president of worldwide field operations, responsible for sales and application engineering for the company's growing roster of customers. He will report directly to Sequence president and CEO, Vic Kulkarni.
Before joining Sequence, Lipinski was director of Silicon Valley sales for Cadence Design Systems, managing major accounts such as Philips, Broadcom, and Nortel. In a 25-year career, he has held a number of senior sales, marketing, and executive posts, including CEO of a venture-capital firm. Direct EDA, computer, and semiconductor experience includes time with Virtual Silicon, Exemplar, Meta Software, Dazix, Computervision, Fairchild, and Gen Rad. He has led efforts to build international sales and support organizations while significantly growing business. At Meta, where he served as vice president of worldwide sales and marketing, Lipinski boosted sales to $35 million before the company's successful IPO in 1995. Lipinski received his bachelor's degree in electrical engineering from Southern Illinois University.
Customer Endorsements
Nassda Corporation announced that Innovative Systems & Technology Corporation (Insyte) is using Nassda's HSIM hierarchical full-chip simulator and analysis tool for verification of SoC integration, custom memories and analog circuits in CMOS and BiCMOS technologies.
Insyte said it purchased multiple HSIM licenses the tool demonstrated superior accuracy and solved performance problems of other tools. Insyte also said it has integrated HSIM into its full-custom design flow, and its engineers now use HSIM for verification of customized embedded SRAMs and analog circuits. HSIM also anchors Insyte's SoC verification flow, where it provides a significant advantage for integration of IP cores in SoC designs, according to the company.
Cadence Design Systems, Inc. announced that S3 / Via Technologies purchased the Palladium design verification system. S3 said it selected Palladium following an extensive evaluation of available simulation-acceleration and in-circuit emulation technologies. S3 said it is using Palladium for hardware/software co-verification of its next generation 3D graphics design, a multi-million-gate chip being implemented in 130-nanometer technology.
Xpedion Design Systems announced that Microtune, Inc., a supplier of RF-based silicon and systems solutions for the global broadband communications, automotive electronics, and wireless connectivity markets, is using Xpedion's GoldenGate RF circuit simulation tools for verification of its RF IC designs. Microtune said GoldenGate allows its designers to utilize Harmonic Balance techniques to analyze and optimize high frequency amplifiers, mixers and oscillators.
GoldenGate tools provide the capability to simulate designs developed in the Cadence Analog Design Environment (ADE) without migration to or from any other format and was given high marks in Microtune's engineering evaluation due to the product's accuracy, ability to converge upon large transistor count devices, speed and unique analysis capabilities, the companies said.
Synplicity, Inc. announced that Toshiba Design & Manufacturing Service Corporation (Toshiba DMS) has standardized on Synplicity's Synplify, Synplify Pro, and the Amplify Physical Optimizer tools. Toshiba DMS, a leading designer and manufacturer of printed circuit boards and designer of semiconductors for communications, control, medical and electronic applications said it chose Synplicity's FPGA synthesis solution to help achieve high quality of results in timing-critical FPGA designs. Toshiba DMS said it would use Synplicity's solutions to design FPGAs for industrial equipment including communications equipment, control systems, medical instruments and electronics equipment.
Toshiba Corporation established Toshiba DMS in November 2001 to reduce printed circuit board design and production costs, which combines the manufacturing and design capabilities of the various Toshiba engineering facilities including the Hino factory, Fuchu business office, Nasu factory, Yanagimachi business office and Komukai factory. Toshiba DMS designs and manufacturers printed circuit boards and designs large scale integration semiconductors and FPGAs.
Corporate News & Partnerships
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) and Synopsys, Inc. have qualified Synopsys' signal integrity (SI) suite to address the design methodology for 130 nanometer (nm) and 90 nm process technologies. This extension of design methodology is the result of an ongoing collaboration to utilize the latest silicon processes. This is the first IC industry collaboration delivering a comprehensive SI suite for 130 nm and 90 nm processes, the companies said.
TSMC and Synopsys have addressed SI issues by deploying a proven methodology using Synopsys' IC implementation and analysis tools coupled with TSMC's manufacturing expertise. The upcoming TSMC Reference Flow 4.0 will reportedly incorporate a number of Synopsys' tools, including Astro, Astro-Rail, Astro-Xtalk, Design Compiler, Floorplan Compiler, Physical Compiler, PrimeTime, PrimeTime SI, and Star-RCXT.
Mentor Graphics extended its remarketing agreement with NewLogic, a leading supplier of semiconductor IP cores for wireless systems, to include the WiLD 802.11 Wireless LAN platform. With this agreement, SoC designers can license a complete platform for wireless LAN IC development from Mentor Graphics. The 802.11 wireless platform complements Universal Serial Bus (USB), Bluetooth and other standards-based IP offerings in the Mentor Graphics Inventra family, enabling the company to further address growth in the consumer electronic, computing and home networking markets.
The WiLD platform includes the multi standard WiLD 802.11a/b/g MAC core and the WiLD 802.11b Modem (physical layer). It will be complemented soon by the WiLD 802.11a and g Modems, the WiLD 802.11a/b/g dual band CMOS Radio and the 802.11e/i/h software upgrade options once the respective standards are ratified, the companies said. In addition, integration support, a prototyping platform (WiLD Card I) and full integration services to help designers meet aggressive time-to-market plans.
Mentor Graphics also announced a joint development and marketing program called ADAPT (Authorized DataFusion Partner), designed to enable Web-based information providers, such as online component database services, to integrate quickly and easily with DMS, Mentor's design data management infrastructure solution. DMS connects the design engineer's desktop to the extended enterprise, making component criteria available during the critical product development phase, in which as much as 80 percent of a product's lifecycle cost is determined.
Mentor Graphics said it would work with ADAPT program partners to develop standards-based interfaces between DMS and the partner's offerings. As a result, Mentor Graphics will be able to offer add-on modules to DMS that will allow users with any necessary subscriptions for the partner's product or service portfolio to incorporate the Web-based information into their company's library.
Mentor also announced that the Global Information Business unit of Arrow Electronics, Inc. is the newest member of the program and the two companies are working together to develop an interface between Mentor's DMS solution and the Global Information Business' leading electronic components database, Ubiquidata. The ADAPT program expands on and formalizes the DMS-Xchange content provider program that Mentor Graphics initially established with PartMiner, Inc.
DMS consolidates and manages the work-in-process design infrastructure, integrates the engineer into the extended enterprise and ensures improved information flow on the designer's desktop. DMS-Xchange is the communication and interchange platform that allows DMS users to access many different content providers and solution partner offerings using standards, such as eXtensible Markup Language (XML) based formats. The modular architecture of DMS-Xchange allows partners to integrate with DMS and gives users the flexibility to choose modules based on their organization's requirements.
ADAPT content and solution providers will be able to deliver a specialized interface to DMS and gain a competitive advantage by making their offerings more valuable to the community of system design and PCB designers using DMS. Companies who are accepted into the ADAPT program sign a joint development and marketing agreement and receive product and technology training. For more information contact adapt@mentor.com.
Synchronicity Inc. and The Virtual Component Exchange (VCX) announced a joint marketing agreement to better connect semiconductor IP vendors to their customers and end users. The agreement extends the companies' existing relationship and leverages Synchronicity's position in design collaboration and IP management with VCX's position as host of the Internet-based regulated trading exchange for semiconductor IP, and supplier of IP exchange software.
Under the agreement, Synchronicity and VCX will market their respective solutions to members of the electronics design chain, which includes library and IP vendors, SOC developers and foundries. The companies will also integrate their applications.
Grand Central Communications announced that Xilinx has chosen its Web Services Network to improve the exchange of critical product test data with IBM Microelectronics. By subscribing to Grand Central's Web Services Network, Xilinx is able to securely integrate with IBM Microelectronics to roll out the company's products. By meeting-in-the middle and connecting to Grand Central's Web Services Network, Xilinx and IBM Microelectronics are able to leverage their existing IT infrastructures, security and file formats without making changes or adding software.
IBM Microelectronics and Xilinx have created a collaborative design and development model that enables the companies' innovations to be taken to market rapidly. Grand Central's network provides a connectivity solution that increases the speed, reliability, and proactive notification of transmission of Xilinx's critical test data from IBM Microelectronics. This improved integration relationship significantly reduces costly chip production issues for Xilinx, resulting in a higher quality product and greater overall productivity, the companies explained.
IBM Microelectronics offers a comprehensive suite of testing services and solutions for chip manufacturers including Xilinx. IBM Microelectronics previously delivering test data to its customers through an FTP link, but now uses this more reliable and secure HTTPS transport protocol.
Events
The 40th Design Automation Conference (DAC) has issued a call for papers for regular technical papers, special topic sessions, panels, tutorials and university design contest entries. The annual conference, which promotes advances in design automation software and hardware for electronic systems, will be held June 2 to 6, 2003 at the Anaheim Convention Center in Anaheim, Calif. Authors are invited to submit original technical papers describing recent and novel research or engineering developments in all areas of design automation for the Design Methods or Design Tools Tracks, or for Embedded Systems Topics. The paper submissions deadline is Friday, December 6. The submission site is scheduled to open Monday, October 21. Panel and special session proposals will be accepted through Monday, November 4, 2002. The panel and special session submission site is now open.
The Student Design Contest is an invitation to students to submit descriptions of original electronic designs, either circuit level or system level. Two categories of designs are eligible for awards -- operational and conceptual. For operational designs, proof-of-implementation is required. A complete simulation is necessary for conceptual designs. Designs must be part of the student's university studies and must have been completed after June 2001. Selected designs will be presented at the conference. Student Design Contest submissions must be submitted by Friday, December 20, 2002.
Notification of acceptance for all will be made by Friday, February 28, 2003. For more information, call (303) 530-4333, or visit the DAC website for more specifics on submission requirements. The site is located at: http://www.dac.com.
The Annual EDA Consortium Phil Kaufman Award Dinner will be held Tuesday, November 12, 2002 at 6:00 P.M. at the San Jose Fairmont Hotel in the Club Regent Room. See www.edac.org for more information.
An upcoming panel of industry CEOs will discuss the benefits, concerns and intricacies of COT design. Companies are looking for ways to design themselves out of the economic crisis, knowing they need to be sharper than the competition. Monterey has put together this panel of electronics industry leaders to address how to reduce risk, maintain security, improve performance and turn around time, and innovate by implementing COT design.
When: Thursday, November 21, 2002 at 4:30 PM
Where: The Westin Hotel in Santa Clara
Registration begins at 4:00 PM. A Q&A discussion with wine and hors d'oeuvres will immediately follow the panel.
Jacques Benkoski, president and CEO of Monterey Design Systems will give a keynote address.
Panelists:
- Mark Templeton, president and CEO, Artisan Components
- Jack Harding, Chairman, president and CEO, eSilicon
- John Bourgoin, Chairman and CEO, MIPS Technologies
- Yoav Nissan-Cohen, Co-CEO, Tower Semiconductor
- Levy Gerzberg, president and CEO, Zoran
- Erach Desai, an electronics analyst with American Technology Research, will moderate the panel.
The first edaForum will take place in Hannover, Germany on December 5th and 6th, 2002. Organized by the edacentrum as part of its mission to overcome the design gap by collaborative actions among system and semiconductor companies, EDA vendors and research institutes, the edaForum02 will bring together decision makers from industry and top-rated speakers from all over the world. Information about the program of this event, the speakers and the location can be found at http://www.edacentrum.de/edaforum.
Mentor Graphics is accepting entries for its 2003 PCB Technology Leadership Awards University Scholarship. Co-sponsored by HP, the scholarship is designed to promote innovation and excellence in education for printed circuit board (PCB) designers at colleges and universities. The winning entry in the Leadership Awards program's University & Training Institutes category receives an academic scholarship totaling $2,000.
The University Scholarship is open to any full-time undergraduate or graduate student (or team of students) at a college or university participating in the Mentor Graphics Worldwide Higher Education Program. A panel of industry-leading expert judges will evaluate each entry for innovation, complexity, physical design and aesthetics. University & Training Category entries are due by December 10, 2002, and award winners will be notified on or before January 31, 2003.
For more information on the Mentor Graphics Higher Education Program and the 2003 PCB Technology Leadership Awards Scholarship visit: www.mentor.com/partners/hep.
To read more news, click here.