There's so much to see at DAC.
The circus atmosphere of the Exhibit Hall floor with the enormous over-sized booths, the exhibitors in matching polo shirts manning their stations, milling attendees streaming up and down the aisles, the magicians, the talent, the barkers, the toys, the nonsense and the noise, and those ever-present and annoyingly loud neon lights, flickering so far overhead that you can't even see them if you try.
Elsewhere in the Convention Center, there's the sacred hush of the padded, labyrinthine corridors of the Demo Suites where secret deals are going down behind very closed doors and you just know that the real stories of the show are being told there, stories you'll never hear – at least for now.
There's the spacious Press Room on the second floor full of old friends, great staff, good cheer, and the ubiquitous – though sometimes lukewarm – coffee, and dozens and dozens of dutiful Press Kits standing ever at attention on long narrow tables that line the walls of the room.
There are endless Panel Discussions in rooms A and B and D – often served up with breakfast or lunch – with easy to understand concepts and lots of people in the audience. And there are Technical Sessions with thinner audiences, but ideas much tougher to grasp and, therefore, more satisfying once mastered. There are keynote addresses with speakers dwarfed by their own images, which are projected onto huge 30-foot screens on either side of the stage, so that the people in the back of the hall can see the color of the tie standing behind the podium.
There are jacketed guards at every door of every venue constantly, constantly checking your badge to be sure that you have earned the right to enter. There are bookstalls and tables full of bottled water and everywhere there are engineers, managers, people, and ideas – many thousands on all counts.
DAC is a complex event and hard to get your arms around.
However, halfway through the fourth of my five days in Anaheim, I happened onto a conversation with five technologists that was as good as it gets at DAC.
Jim Lipman's Wednesday panel started at 7:30 AM and had just concluded a 2-hour discussion of what's wrong with front-end to back-end hand-off. Many people had already rushed off to their next meeting or session.
But a few lingered on in Room 213A, and suddenly I was confronted with a set of business cards and an even more imposing set of intellects determined to dissuade me from my stated lament that no matter how clearly tool users articulate their needs, it seems EDA vendors stubbornly refuse to listen.
John Sanguinetti, Forte Design, was somber and direct in telling me that I was completely underestimating the seriousness of the problems facing EDA tool developers. “The reason that EDA tools don't solve all of the users' problems is because these problems are really tough.” His was a message of reprimand for me and anyone else foolish enough to try to simplify the long-standing challenges that have characterized CAD tool development for integrated circuit design.
Magma's Arvind Srinivasan tried to soften the message by assuring me that serious conversation happens on a daily basis between EDA tool vendors and their customers. “The phone calls are really flying back and forth every day.” He asked politely, but firmly, that I give credit where credit is due to the vendors who are trying so hard to meet their customers' needs.
Cadence's Eric Filseth said that vendors regularly face lots of tough questions from customers in one-on-one meetings, and that I needed to remain ever cognizant of the time lag between EDA tool development and EDA tool deployment.
He recounted a story, perhaps apocryphal but meaningful nonetheless, of a user who had carefully detailed his needs to a major EDA vendor. The vendor promised to get back to the user within 6 months with a solution. After 6 months, no solution was forthcoming. The vendor admitted that the problem was more difficult than he had initially thought, and asked for another 6 months. Again, however, no solution was forthcoming after the allotted time. The vendor said now he understood that the problem was really, really difficult and needed yet 6 more months.
After those additional 6 months, the required tool and functionality were finally delivered. Unfortunately by that time, as could have been predicted, the tool was no longer relevant. The technological aspects of the problem had evolved and the tool was essentially obsolete. Having seen this happen so many times, Filseth said, “Now I'm a nihilist when it comes to EDA.”
Magma's Yatin Trivedi (previously with Intrinsix) said, “The users' problems are a moving target. They're always changing even while we're trying to solve them.”
So I asked about a different strategy. Why don't designers and design houses just develop their own tools as their needs develop? Wouldn't that be much more efficient, producing solutions specific to each problem?
NEC's Wolfgang Roethig, said, “Internal CAD tool development at user companies is dead. It doesn't work. Now we're relying on the EDA industry to solve the problems.”
Srinivasan said, in any case, my strategy would be reducing, not increasing, efficiencies. He said it's a matter of keeping track of global solutions versus local solutions. Many users have the same or similar technical hurdles to get over, and tool vendors can provide the means to confront those hurdles with similar tools, albeit customized at times to address a particular end-user's needs.
I said that after wandering through many company meetings and booths at DAC – companies with only 10 or 20 employees – the whole business model seemed so wasteful. Why not join forces across all of EDA? I told them how frustrating it is to see so many great minds (well, maybe I didn't use the word “great,” but they knew what I meant) scattered across so many small companies, all seemingly at work on the same or similar problems. Why not join them all together in a great army of talent and knowledge, and have them work to solve the design issues in one concerted, integrated, and inspired effort?
Trivedi said, “Do you mean something like EDA, Inc.? Well, that's a great idea – but only if I get to be the boss.”
Sanguinetti said, “Small companies are the only place where innovation takes place. Big companies aren't the answer.”
I asked then, why do the large EDA vendors always seem to want to control the flow? Is that possible and why do they want to do that?
Several people standing in front of me said that no one vendor can own the flow, that it takes multiple vendors to provide all the necessary tools.
But Filseth said, “Actually, if you have a very small, very slow chip, you can design it with one flow – the Synopsys flow, now that Avanti is part of it.”
Roethig said, “Yes, but for high-end designs you still need lots of vendors, lots of tools. But, you also need standards. That's where the solution for the EDA vendors will be found. That's how you get the best tools.”
Several in the group were less than enthused. Sanguinetti said standards can often be counter-productive. Filseth mentioned the oft-cited VHS/Beta standards war that proved that “lesser” technologies sometimes win.
Sanguinetti countered, “Do you know why Beta failed? Because you couldn't record an entire football game on one tape. It was that simple.”
I referred to EDA, Inc. once again and said I wasn't trying to suggest that non-competitive, anti-free market strategies would solve the problems. I acknowledged that motivation often comes in the form of profits, particularly in small companies, should they be successful.
Sanguinetti corrected me one last time. “Engineers aren't really motivated to innovate by money. They're motivated by interesting problems.”
Srinivasan agreed. He cited many people within EDA who have already made their fortunes, but continue to work 14-hour days. “Engineers want to solve problems. They don't start EDA companies because they think they'll make a lot of money. They're just thinking about the engineering and the interesting challenges in all of it.”
Many minutes had ticked by. The 10 o'clock hour drew nigh. Many had meetings, sessions, other appointments. I told them that this was not the first time I'd been reprimanded for pointing out the muddle & meandering that I sometimes sense across the EDA landscape.
The 5 of them seized the opportunity to drive home their point.
“EDA is full of really smart people.”
“The tools are evolving and getting better.”
“The industry is committed to moving forward.”
“EDA wouldn't be fun if all of the challenges were solved.”
I told them that their persistent message of optimism about EDA and the way it is structured for innovation, etc. was something good. I told them that they should take their show on the road.
Roethig said, “Yeah, we could do that. We could have a panel discussion and you could moderate it.”
I said, “I think I just did.”
We all shook hands and went our separate ways.
I rode one of the many long, thin escalators down to the first floor to get my morning mocha. As I glided down alongside the 5-story windows that define the west wall of the building, I looked out over the many tall palm trees swaying slightly in the morning breeze. There are over a hundred of them – I counted – lining the paths and gardens between the Convention Center and the adjoining hotel complex.
I thought about how the palm fronds at the top touch each other in the breeze, from tree to tree, green and pleasing and free, to create an integrated canopy overlooking the patio below. I thought about the stern, rigid trunks that support that canopy. I was looking right at those trunks now, as the escalator reached the first floor.
Isn't there a corollary there, I thought. The pretty, appealing fronds way up high, all interacting with each other, partnering, and aligning, and re-aligning – making swishing noises in the wind. Aren't they just like the sales and marketing and management portions of EDA – the pretty and noisy portions.
But the sturdy, unbending trunks of the palms below – aren't those the engineers. Look how they think in straight and rational ways about how to conduct the water up to the fronds, how to withstand the stresses of wind and weather, how to extract and deliver nutrition to the system. The trunks are the problem solvers. They're there because they love the challenge of it all. They never fall down on the job. They don't look at all like the fronds. They don't swish and sway. And they're definitely not very pretty.
The palm fronds are pretty and fun and eye-catching. They make it all worthwhile by helping the trunks to focus on an end goal. But when the fronds tire, they wilt or drop. The trunks never do.
EDA is based on technology. It is based on science and engineering and rigorous research and development. Let's not forget, no matter how fun the party, how glib the marketing message, how choreographed the press conference, how clever the business partnering, the mergers, the acquisitions, the investments, the stock valuations – the trunks are the sturdy part of the garden.
The engineers continue to support the canopy because the problems continue to fascinate them and tax their intellectual abilities. They're having a wonderful time in a way the fronds will never understand. The fronds would be nothing without them. Absolutely nothing.
Industry news – EDA and IP
Agilent Technologies Inc. announced that Agere Systems selected the Agilent RFDE (radio frequency design environment) to develop Agere's RF/mixed signal IC design flow. The companies say the new design flow will allow Agere designers to model and simulate high-frequency effects in new chip designs with “greater speed, accuracy and efficiency.”
Analog Design Automation, Inc. (ADA) announced that the company has partnered with several layout vendors to integrate ADA's front-end optimization tools with a range of layout tools. The first announced partner vendors are CiHraNova, Sagantec, and Silicon Canvas. The company says that “the partnerships are designed to reduce the time spent on the analog portion of IC design by enabling designers to focus on the design process rather than interoperability issues. This will help ensure that customers are provided a consistent flow between ADA's Genius optimization tool suite and the customer's choice of layout partners.”
Ansoft Corp. has released the AnsoftLinks v2.5 interface for the Cadence Virtuoso digital and analog custom IC layout editor. The companies say the interface makes it possible to export circuit layout cells from within Virtuoso to Ansoft's EM analysis tools. Ansoft is a member of the Cadence Connections Program.
ARC International announced that iStor Networks licensed the ARCtangent-A4TM, user-customizable RISC processor plus software and development tools in the development of its iSNP8000 (IP storage network processor).
Cadence Design Systems, Inc. announced that Taiwan Semiconductor Manufacturing Company, Ltd. has adopted the Cadence Encounter digital IC design platform as a part of TSMC's new Reference Flow 4.0. The companies say this move is part of their collaborative efforts “to optimize the silicon design chain for mutual customers by addressing difficult nanometer design challenges, such as full-chip signal integrity closure.”
Chip Express, Inc. and Synplicity Inc. announced that Chip Express has endorsed Synplicity's Synplify ASIC software within its structured ASIC flow. Doug Bailey, Vice President of Marketing at Chip Express, said, “FPGA and ASIC design tools and methodologies have taken divergent paths. Designers are already familiar with Synplicity's Synplify software for FPGA design. With the customized version of our libraries for the Synplify ASIC software, designers can more easily tie together FPGA and ASIC designs and easily transition to structured arrays without learning to use different tools and platforms.” Interesting news on the heels of Synplicity's recent announcements with LSI Logic.
CoWare Inc. and Novas Software announced they are collaborating to deliver an “integration roadmap between their tools” and bring Novas' debug technology to SystemC. The companies will create a link between CoWare's ConvergenSC tools and Novas' Debussy debug system, which the companies say will allow designers to debug SystemC, Verilog, and VHDL in a common environment for SystemC and HDL flows.
Also from CoWare – The company announced that it will also work with Verisity to produce an integration roadmap for the companies' products. (See Verisity announcement below.)
Denali Software, Inc. announced that it is now offering configurable IP cores for PCI Express technology. The PCI Express core was developed and verified by IBM for use in its own ASICs, foundry, and standard product designs. Denali will directly sell and support application specific configurations of the core through its own channels along with its existing PureSpec verification IP product for PCI Express.
Golden Gate Technology Inc. announced GoPower to “completely address the long-neglected problem of low-power layout.” The tool contains a floorplanner, a power grid synthesis and automatic placer to permit a power-driving architectural approach to physical design. Oki Semiconductor endorsed results they've achieved through use of the tool.
Incentia Design Systems, Inc. announced performance improvements in TimeCraft, a static timing analyzer. The company says the new release “improves its runtime up to 5x and reduces memory utilization up to 30% on large designs, when compared to the previous release.”
iRoC Technologies announced the completion of a series of radiation tests at several neutron and proton facilities on SRAM, DRAM Flash, and TCAM memory types to measure soft error rates (SER). The company says that for 0.13-micron technologies and below, soft error rates for test die are necessary to verify the compliance with quality and reliability specifications.
Magma Design Automation Inc. announced the company has completed a comparative study of TSMC's libraries with six variations of the 0.13-micron process node with a “widely used embedded microprocessor core.” Magma worked with TSMC's Design Services Division to qualify timing, RC extractions, and DRC.
Monterey Design Systems announced the initial release of the Calypso silicon virtual prototyping (SVP) system. The company says Calypso is built on Monterey's progressive refinement technology, and that Calypso is the first SVP system to include both hierarchical design planning and physical prototyping in a single tool. The system combines hierarchical design planning, physical synthesis, and physical prototyping in a single tool built on top of a hierarchical database, to allow for optimizing the timing of a path that spans multiple blocks without having to go into each individual block and optimize each sub-path contained within the timing path. It also provides analysis so that
if the power rail is widened at the chip-level, the tool can measure the effect on IR drop incrementally inside all of the blocks.
Pulsic Ltd. announced the Prelude Physical Design Framework, a shape-based, high-capacity IC physical design framework for very large digital/ASIC designs. The company says the tool includes an ECO placement and routing capability, “powered” by scalable architecture, that uses a true distributed computing environment. The framework is characterized by a compact database for handling millions of nets using a memory footprint of less than 1GB per 1 million nets or cells, placement capabilities including the ability to shove cells aside to make space for new or relocated instance, and support for “leading” DSM rules and processes including slotting and 45-degree/free-angle routing rules.
Random Logic Corp. announced QuickIND, a physically based inductance-extraction tool for the design of complex ICs based on “novel” stochastic methods. The company says the tool is well suited for high-speed digital, mixed-signal, and wireless RF design applications. Random Logic's tool suite now addresses three basic electrical circuit properties, resistance, inductance, and capacitance, which allows full RLC interconnect analysis. QuickIND can run fully parallel on multiple computers.
Synopsys, Inc. announced Galaxy SI, a new signal integrity tool within the Galaxy Design Platform that addresses crosstalk delay, noise, IR drop and electromigration. The company says Galaxy SI provides designers with “comprehensive prevention, analysis and sign-off, speeding SI closure for 130-nanometer designs and below.”
The company also says in introducing the tool that existing SI solutions are incomplete, offering a mix of point tools or reliance on third-party sign-off, which can result in delayed SI closure. Synopsys' Galaxy SI is an integrated platform with SI support at all stages of the design flow, from implementation. Galaxy SI uses PrimeTime's golden delay calculator and common design infrastructure - common libraries, constraints, and database. Galaxy SI is easy to adopt because it is built into the Galaxy Design Platform. Jean-Pierre Geronimi, director of Computer Aided Design, STMicroelectronics R&D, said, “We used Galaxy SI in our UNICAD design environment for signal integrity prevention and
sign-off of our 120-nanometer production designs, and have now adopted the solution for our next-generation 90-nanometer designs.”
Also from Synopsys – The company announced that the Galaxy Design Platform and other Synopsys tools have been integrated in TSMC's advanced Reference Flow 4.0.
Finally from Synopsys – The company announced that Toshiba has standardized on Star-RCXT as the parasitic extraction tool for its 90-nanometer TC300 design technology.
TransEDA PLC announced the availability of PA-Studio, a property and assertion capture and validation tool. The company says the tool supporting standardization of the new Accellera PSL (Property Specification Language), formerly known as IBM Sugar, as the de facto language for property development. PA-Studio allows designers to graphically create, verify, and debug properties and assertions. It has a drag-and-drop facility to capture properties from signals that appear in a design's hierarchy, so that designers do not need to have an in-depth knowledge of the PSL/Sugar language in order to generate properties.
TSMC introduced Reference Flow 4.0 at DAC 2003, a flow TSMC says is “the industry's first complete design flow that responds specifically to nanometer design challenges and features dual physical implementation tracks built around commercial EDA tools primarily from Synopsys, Inc. and Cadence Design Systems.” (See news items above from Synopsys and Cadence.)
The Press Release says, “Reference Flow 4.0 provides IC design teams with the flexibility to tap into TSMC's recommended design methodologies independent of tool preferences, while directly addressing technical challenges related to designing at 0.13 micron and 90 nanometers. The era of nanometer design will be marked by SoC devices with higher circuit complexity, increased I/O counts, faster clock speeds, and highly integrated IP blocks. Implementing these designs requires tight integration of design methodologies and advanced processes. Reference Flow 4.0 bridges the gap between design and silicon to provide significant time-to-market advantages.”
If anyone has doubted the impact the foundries are having on the whole semiconductor landscape, and EDA in particular, they should go study the TSMC Reference Flow 4.0 in greater detail. There is a good reason why the EDA vendors want to be aligned with TSMC and the other major foundries in the business. The question might even be asked as to who is actually driving design these days – the customers, the EDA vendors, or the foundries. I'll bet not everyone will agree on the answer to this query.
Verisity, Ltd. and 0-In Design Automation announced they are collaborating to provide reporting of integrated verification coverage metrics for their joint customers. The coverage information available in Verisity's Specman Elite testbench tool will include both native functional coverage metrics and the structural coverage metrics from 0-In's CheckerWare assertion checkers and monitors. The companies note that testbenches and assertion-based verification (ABV) are complementary approaches.
The Press Release says: “One very important aspect of complex chip functional verification is the use of coverage metrics to identify next steps at each stage of the verification process. This leads to coverage-driven verification, in which verification 'holes' are identified from the coverage metrics and then improvements in the metrics gauge the effectiveness of additional effort. Within a Specman Elite-based verification flow, users can examine all forms of coverage metrics to assess areas of
functionality not sufficiently exercised, adapt the constraints for pseudo-random test generation to exercise these areas, and then validate the effect by looking at the revised metrics. Within the 0-In verification flow, the structural coverage metric plays three roles. The metric helps the users identify verification hot spots, exercise these hot spots in simulation and measure the results, and confirm that the hot spots are fully verified with formal methods. The combined capabilities of the Verisity and 0-In tools allow users to measure whether there are enough assertions in the design, how well the design is exercised in simulation and how much additional confirmation has been provided by formal verification.”
X-FAB UK Ltd. announced that one of three manufacturing sites belonging to X-FAB Semiconductor Foundries AG, has been awarded certification according to ISO TS 16949. The Press Release says, “The quality standard ISO TS 16949 standardizes automotive industry requirements for both Europe and the USA and it is expected that the technical specification will become the common and unique basis for the automotive industry's quality management system requirements worldwide, gradually replacing the multiple national specifications now used by the automotive sector.”
The X Initiative announced that Applied Materials, Inc. produced the first 90-nanometer test chip for X Architecture interconnect designs at its Maydan Technology Center in Sunnyvale, CA. The announcement says “the fabricated test chip validates design rules and the manufacturability of X Architecture interconnect designs for copper/low-k chips using existing mask making and wafer processing technologies.”
Newsmakers
Yet Another Industry Consortium – The SPIRIT Consortium says it is focused on increasing efficiency through standards for IP packaging and IP Tools. The consortium was announced at DAC and has 7 charter members, including ARM, Beach Solutions, Cadence Design Systems Inc., Mentor Graphics, Royal Philips Electronics, STMicroelectronics, and Synopsys Inc.
The member companies say the consortium will help to develop industry standards that will enable easier integration of IP and IP tools, and will focus on developing standards for describing and packaging IP in order to cut costs, increase ease of use and enable greater flexibility in selecting and integrating IP. (SPIRIT stands for Structure for Packaging, Integrating and Re-using IP within Tool-flows.)
Now, this may all sound vaguely like another consortium that's already been around for a number of years. I asked Ralph von Vignau, SPIRIT consortium chairman, about VSIA immediately after the SPIRIT press conference in Anaheim. He said he had a meeting planned for the very next day with the VSIA people.
He also said, “VSIA is an open-standards group with companies, students, professors, and universities all discussing IP issues. It has not managed to focus, however, on bringing things to market. There's been some frustration there. We will have seven companies in SPIRIT. Other companies can join this consortium, as well, but the seven companies will be like the Security Council. We will have veto over any final decisions. The companies in SPIRIT are in EDA and IP and these are the people who can solve the IP problems of today. This is a pilot project with everyone taking a little bit of the load, and we hope to publish our first documentation by the end of 2003.”
Cadence announced the donation of comprehensive and portable Verilog language extensions to the IEEE. The company says the donation was “driven by customer requests.” Cadence also announced comprehensive support for the IEEE 1364-2001 standard within the Cadence Incisive verification platform.
As part of its donation, Cadence provided a testbench implementation as a functioning prototype for the IEEE and EDA product developers. The implementation will be available for free, downloaded as a Verilog Procedural Interface (VPI) binary library that can be used with any IEEE 1364-compliant simulator. The Press Release says, “Engineers now can develop advanced testbenches in Verilog, confidant that their code will function consistently on all simulators.”
Monterey Design Systems announced the Monterey Calypso Vanguard program, developed in conjunction with member companies, to address the rising cost of designing multi-million gate chips and the severe penalties of making uninformed decisions early in the design cycle. The program is designed to provide members with information such as choice of process technology, choice of IP blocks, architecture, power and clocking schemes, and chip-level design plans, so that these choices can be made early on in the design cycle. The program will provide members with early access to Monterey's Progressive Refinement technology and future products, which the company says will allow member companies
to validate the compatibility of their IP elements with the Monterey technology. Charter members include Toshiba, Ricoh, and Fujitsu.
Verisity Ltd. announced that the IEEE Design Automation Standards Committee (DASC) has approved a project to use the e verification language as a basis for standardization. Verisity says this marks a significant step for the verification industry, as e is now the first verification language to be considered by the IEEE. In addition, DASC standards have an expedited path to the International Electrotechnical Commission (IEC) submission process, facilitating further international adoption of DASC standards. Paul Menchini, Chair, IEEE Design Automation Standards Committee, said, “I'm delighted to see such strong interest in developing a verification language standard and from such a broad
cross-section of the industry. Such interest is one of the core necessities for a successful standard. We thank the Verification Language Study Group (VLSG) and the DASC for their hard work in taking these important first steps towards standardization.”
In related news, Verisity announced it supports a wide variety of open standards including OVL, PSL/Sugar and SystemC. Verisity will support PSL/Sugar as an assertion language and SystemC as a design language. In addition, Verisity also announced a new Coverage and Assertion Interface (CAI) that allows users to import external coverage metrics and assertions into Specman Elite for coverage and error analysis. The company says this will enable verification engineers to use a variety of coverage metrics, such as functional, assertion, code and formal coverage, in order to drive their verification methodology.
The X Initiative announced the 2003-2004 steering group for 2003-2004. Members of the group include Pallab Chatterjee, President and Managing Partner, SiliconMap, LLC; Kevin Cummings, Director for Advanced Reticle Technology, ASML; John Ford, Vice President of Marketing, Virtual Silicon Technology, Inc.; Aki Fujimara, Corporate Vice President and General Manager of Design for Manufacturing, Cadence Design Systems, Inc.; Jim Jordan, Director, Business Development, DuPont Photomasks, Inc.; Takashi Mitsuhashi, Chief Specialist of LSI System Design, Toshiba Corp.; Chris Rowen, President and CEO, Tensilica, Inc.; R. L. Smith, Director of
Strategic Marketing, Etec Systems, Inc., an Applied Materials, Inc. company; and Jan Willis, who returns as steering group facilitator. Willis is Vice President of Strategic Third-party Programs at Cadence Design Systems.
The X-Initiative is a semiconductor supply-chain consortium chartered with accelerating the availability and fabrication of the X Architecture. The X Architecture Press Release says the initiative “represents a new way of orienting a chip's maze of microscopic wires using diagonal pathways, as well as the traditional right-angle, or 'Manhattan, configuration. By enabling designs with significantly less wire and fewer vias, or connectors between wiring layers, the X Architecture can provide significant improvement in chip performance, power consumption and cost.”
In related news, the consortium announced that STMicroelectronics is the recipient of the X Initiative's 2003 DFM (design for manufacturing) Catalyst Award. The X Initiative steering group says it selected STMicroelectronics from the 37 member companies as having made the most significant contribution to the design-for-manufacturing goals of the X Initiative during the past year.
In the category of ...
It's a mystery why everyone has to focus on finding just one or two themes at DAC. Aren't there many themes, some more important than others, some more long-lived than others?
Here are some additional themes that might be added to the list of other Issues at DAC previously touched upon in earlier issues of EDA Weekly.
The topics below are among the many I heard mentioned in Anaheim. Again, these are only snapshots of the complex ideas swirling about in the technology. Much, much more could be said on each topic, and many, many more issues could be cited, but space and time are limited.
Issues at DAC – Virtual Silicon Prototypes
The great annual Dataquest kick-off presentation always takes place on Sunday evening, before DAC begins the next morning. This year, hundreds and hundreds of people were there to hear the various analysts present their prognostications for 2003. Unfortunately, I was not one of them, as my breezy road trip down from Northern California was not quite breezy enough. I arrived at the Sunday night session just as it was ending.
Fortunately, Dataquest's Daya Nadamuni was kind enough to give me some time several days later to recap the highlights of the presentation and to give me her impressions of DAC 2003 up to that point in the show.
“I've felt a breath of optimism on the show flow, the light at the end of the tunnel. I'd guess from that, and from the information presented on Sunday night, that the rebound has started – or will start soon. We're seeing about an 8% growth in EDA for 2003, with substantial growth out there in 2005. In between, we think 2004 should be good – not blockbuster – but good.”
“Meanwhile, we think there will be continued consolidation in EDA either through merger or acquisitions. Although, I am encouraged to see a number of new start-ups. These new companies are doing all sorts of things – design for yield, for instance. Particularly when you move from one process generation to the next, you see customers tying to figure out what to do, and the tools and methodologies trying to figure out how to approach that market. EDA companies need to continue to try to understand their customers and what kind of support their customers need. Meanwhile, we see three types of customers [differentiated] by their CAD-tool budgets, the kinds of designs they're doing, or the amount of control they need over their internal CAD teams.”
“And the rumors you are hearing are correct. Gary Smith told people on Sunday that silicon virtual prototyping for RTL hand-off will be important, and that ESL tools will be important as well.”
Soon after this conversation, I happened to find myself in a meeting with TenisonEDA, a company based in Cambridge, U.K. I was still focused on Daya's comments about virtual silicon prototyping, so when CEO Jeremy Bennett mentioned the concept. I asked him to elaborate on a specific definition, one that could help me more fully understand why virtual silicon prototyping was getting so much buzz at DAC.
Jeremy said, “I was at the Dataquest event on Sunday, and I was very pleased to hear Gary Smith specifically mention 'virtual silicon.' Although my definition of the concept is broader than Gary's, it aligns with our technical view of the world perfectly.”
“For Gary, it's a low-level model of silicon that allows you to get to timing issues in the design. That's one view that works with the ESL [electronic system level] designs. But, in reality you need virtual silicon at all levels in the design process.”
“In our view, virtual silicon is also defined as 2-value, cycle-accurate models of the silicon. That is specifically for the firmware engineer working in the software environment. On an SoC, there's actually 2x to 3x engineering effort required for software, as there is hardware. So there's a particular type of virtual silicon that's needed in software development.”
“Software and firmware developers don't need low-level modelling of the hardware – they only need noughts ['Brit-speak' for zeroes] and ones to understand if their software is working.”
“So I would put virtual silicon across a spectrum, which means that Gary and I are both right. There's virtual silicon at every level – for example at the instruction-set simulation level, at the cycle accurate modelling level, as well as the detailed electronic level.”
“The reason that everyone is talking about virtual silicon is the SoC. In the past, silicon was simpler and its functionality stood alone. But now, the point is that every chip is effectively an SoC and software is critical to the operation of the chip as a system.”
“Writing the software requires cycle-accurate models of the chip on which it will run. This 'virtual silicon' allows software development to begin as early as possible in the design process. In the past, such models were created by hand, with power users employing their own modelling teams in-house.”
“Now, however, at 90 nanometers, the chips have 100 million gates. When your design has 100 million gates, you can hardly write a model by hand. Hence the emergence of specialist tools from vendors such as TenisonEDA to meet that need.”
(Editor's Note: It's not clear how to distinguish between “silicon virtual prototyping” and “virtual silicon prototyping.” Are they one-in-the-same or distinctly different?)
Issues at DAC – Partnering and Power
Tuesday morning at DAC, I had a chance to converse with Ron Nikel, CTO of TriCN and Brani Buric, Senior Director of Product Market at Virage Logic in a jointly held briefing. The two companies are partnering in a serious way.
We started by discussing the partnering issues that had been mentioned in depth by ARM's Sir Robin Saxby in his keynote address earlier in the morning. Clearly the two companies agree about the need for partnering across corporate firewalls and this particular partnership seems to be benefiting both companies. Let Sir Robin extol the virtues of partnering. Let him explain how partnering requires trust and openness, contracts, confidentiality, and regular meetings to minimize miscues. These two companies, TriCN and Virage, are executing on the theory in tangible and constructive ways.
The results of the partnership has been the creation of a Base I/O library compatible with both the Virage semiconductor IP platform and TriCN's portfolio of high performance interface products – the I/O library is available for purchase from both companies.
Virage Logic's Buric said, "Partnerships have to be viable on both the business level and the technology level to make sense to the companies involved. And they can't just be a result of reactions to a perceived problem up ahead. Partnerships have to emerge as a result of producing real solutions to real world problems. Companies need to have common goals and a good perception of what makes sense from a business perspective."
TriCN's Nikel said, "We've admired Virage for a long time as an example of how to successfully grow an IP company. We've viewed their ability to dominate the memory space as a model for how we would like to dominate the I/O space. Given our synergistic product portfolios, working together made a lot of sense."
Ron Nikel went on to explain his take on the current crisis in power management in high-end designs: “'Power' seems to be the new buzzword here at DAC, as if this is a problem that has just emerged on the horizon with the latest geometries. But the potential concerns related to power have been evident for some time now.”
“Most people think that the main power issue at 130 nanometers is static power. In fact, dynamic power creates just as big a problem at both 130 and 90 nanometers, due to the increased power density caused by increases in transistor density and higher clock frequencies. A large amount of dynamic power can create huge issues with heat dissipation, and if it's dealt with ineffectively, it can result in huge packaging costs.”
“So power management is a worthy goal for any number of reasons. By reducing a chip's total DC requirements, the thermal characteristics are also reduced, which results in longer reliability for the product. You also increase the reliability of predictions, as higher dynamic power and behavior results in IR drops and timing that is out of line.”
“We are continually addressing power issues as they relate to high performance interface development. For example, in the area of multi-gigabit SerDes design, traditional analog design creates enormous demands for power consumption. We recognized this several years ago and developed an all-digital SerDes design that has significantly reduced power demands versus an analog alternative design.”
“As the industry moves to even smaller geometries – 90 nanometers and below – what types of companies are going to be first on the scene? The most likely ones are those who gain the most from small real estate and high performance, such as producers of WiFi or Bluetooth products. Of course, power conservation will be very high on their list of issues with which to contend.”
“Clearly, technology partnerships are going to become more important in dealing with the challenges brought on by those technology advancements. Given that smaller geometries will have longer turn-around times and higher mask costs, companies making the move to the next technology nodes will need to rely more and more on outsourced IP products to reduce time to market and risk.”
“The development of our Base I/O library is a good example of how we worked with partners – in this case, Virage Logic – to anticipate and help address customer issues, including power. We created this library because we recognized that existing libraries in the market required significant re-engineering to manage the demands of high performance design. The TriCN team consulted with Virage on the optimal way to address power, ground, and noise isolation issues, among others. The Base I/O library helps meet our customers' demands for performance as they increase, and is also a building block for a broader set of products that includes the Semiconductor IP Platform offered by Virage and the TriCN high performance interface IP portfolio.”
I think Sir Robin would be proud.
Issues at DAC – Italian Zest and the many flavors of SPICE
As compelling as Saxby's keynote was on Tuesday morning, Alberto Sangiovanni-Vincentelli's talk was even more so, as he wrapped up DAC 2003 with the closing keynote on Thursday afternoon.
It was a rollicking hour of history, philosophy, technology, economics, not to mention Italian sparkle and charm. Even if you weren't a technologist, you would have been caught up in Alberto's zest for life. If you were a technologist, you would have found his talk riveting – particularly if you're interested in how we got from there to here in EDA.
You should know that, thanks to the magic of modern computing and data storage, the ENTIRE 40 years of DAC proceedings is now available on a single DVD, and in fact, was included with the conference materials given out in Anaheim. Think about what this means. Think about 40 of those 20-pound tomes that have been gathering dust on your bookshelves. Think about the technology advances that have had to occur in order to achieve this level of information density. It is nothing short of spectacular. Mind-boggling, really.
Take that sense of wonder and whimsy, apply it to an IEEE fellow, long-standing faculty member of the EECS Department at U.C. Berkeley, and someone who helped to found both Synopsys and Cadence – and you'll see why, when Alberto accepted DAC Chair Ian Getreu's invitation to deliver a keynote summarizing the 40-years-of-DAC DVD, it was destined to be an unforgettable moment in the annals of DAC keynote speeches. After all, Alberto himself wrote a part of that 40-year EDA history.
More details later, but for now – let's just dwell on one piece of that history that was mentioned in Alberto's talk, something associated with U.C. Berkeley, as well. It's the workhorse of IC design, the SPICE simulator. Even before the keynote on Thursday, I happened to be in a meeting with Dima Smolyansky, Product Marketing Manager for TDA Systems, and got into a discussion about SPICE. I asked Dima why SPICE, which could be characterized as a fairly old technology, remains the lynchpin of signal integrity simulations even today?
Dima told me that it is important to TDA that they remain vendor neutral on this topic. Nonetheless he offered these comments: “The original SPICE, the Berkeley SPICE, is in fact an old technology. The commercial versions of SPICE, however, have evolved substantially. The simulation algorithms have been optimized to run faster and to intelligently select the simulation step and tolerance. Very powerful schematic capture tools have been developed, and large libraries of active and passive components now come with SPICE tools. Some SPICEs are capable of handling frequency dependent losses, and some even claim to be able to handle the frequency dependent S-parameters.”
“At TDA, we approach this question from an interconnect analysis prospective, of course. We provide Berkeley SPICE free with our IConnect software. Although, we think that without IConnect driving it, Berkeley SPICE is not a very friendly tool. We also find that Berkeley SPICE can simulate some circuits a lot more slowly than Hspice or Pspice (other simulation tools to which we provide integrated interfaces).”
“And, of course, we must use IConnect modeling algorithms to explicitly convert frequency dependent transmission line data into simple behavioral models, which Berkeley SPICE can understand and simulate. On the other hand, with Hspice, we can give the user a choice between the parametric (W-element) or behavioral models, allowing them to make a trade off between simulation speed and accuracy.”
Issues at DAC – Breaking into the U.S. Market
The EDA Consortium is based in Silicon Valley and they are a pivotal sponsor at DAC. If a company wants to participate in EDAC-sponsored events in non-DAC weeks, however, they must either maintain an office in Silicon Valley, or be ready to hop onto a plane (often on a moment's notice) to send a representative to such events.
However, there are a number of plucky EDA vendors that are not only not based on the West Coast, they're not even based in the U.S. Among the challenges that they share with EDA companies everywhere – identifying viable customers, competing with the larger players, convincing potential customers of their staying power – 'foreign' tool vendors often also face the daunting problem of breaking into the U.S. design market in the first place.
Lars-Eric Lundgren is President and CEO of Hardi Electronics AB, based in Lund, Sweden. He's an articulate spokesman for the company – which has been in business since 1987 and today sells a high-speed ASIC prototyping system – and was willing to engage in a candid conversation during an afternoon meeting at DAC about the difficulties of gaining a foothold in the American market.
Lundgren said, “After being in the EDA tools business for nearly 20 years, I have seen many companies try to get into the U.S. market and fail. In fact, I think this is true for many other technology areas, as well – not just EDA.”
“What is the reason for these difficulties? The answer probably has to do with what people are used to, the habits they follow [in their purchasing decisions]. An American company is used to buying from Americans. It's closer, feels safe, and [the package says], 'Made in the U.S.A.' This is especially true for tools for the electronic design community. Most EDA tools today are from the U.S.”
“However, it is interesting to look at other industries, for instance the automobile industry, [that have benefited from a less American-centric business focus]. The U.S. used to be quite self-supporting in the automobile market. However, some years back, it became a well-known fact that foreign cars – non-American cars – were of a higher quality than U.S. cars. At that point, some Japanese and European cars successfully entered the U.S. market. The competition got tougher across the automobile industry as a result, and U.S. car manufactures were forced to [create products] that were of a much higher quality. This is [interesting] proof that it is very good for U.S. markets [and U.S. consumers] to be open to non-U.S. companies.”
“So what is the recipe for success in the U.S. for non-American vendors trying to break into the market?”
“The first thing – which is a must – is that the quality of the product must be of a higher quality than competing products made in the U.S. Secondly, the product must exist and be fully functional. This sounds like a strange comment to make, but in my experience, many U.S. companies first do the marketing, then develop the product.”
“A third, often-discussed factor for success is providing local support for the product. U.S. companies demand [domestic support] for the products they purchase. One could argue that it doesn't matter where the support comes from as long as it is good and fast, but in reality, that is probably not enough. So it's very important to be honest with an American customer.”
“Don't talk about how many fancy offices you will open soon. Don't try to give the impression that you will cover the entire country this week. It's a huge country and a huge market. Instead, it is important to explain to the customer that it will take a while to support everyone locally and that it will depend on how well the products are received. Then explain how the support will be provided.”
“When selling U.S.-made EDA tools in Sweden, for instance, I have had very good experience in working with suppliers in the U.S. You send an email [to the vendor] in the afternoon, and the next morning you get a solution to your problem. In fact, that [process] might have taken a whole working hour in real-time in Sweden. But the guys in the U.S. fixed the problem while I was sleeping.”
“So tell the customer about this advantage. And he might also understand that it is better to get a solution [directly] from the developer of the system then to have a middleman trying to understand the problem and send it on.
“Of course, it is extremely important that you have a fast and VERY high level of good technical support. You must always be able to answer a phone call or an e-mail quickly – at least in those hours when both countries are [hard at work]. And even though an e-mail hotline around the clock is expensive, it is a very good service [to provide]. It will also be a key factor that your people who are working in support are very skilled [with the tool and the technology]. Therefore, I would recommend that the developers themselves take turns on the hotline in support of the tools.”
“So, to break into the American market, have the best product, work hard, and have a high level of technical expertise. [If you do this], you will succeed in the U.S. Good luck!”
I think Lars-Eric meant luck has nothing to do with it.
Ending on an eclectic note
Meanwhile, say you were facing Dataquest's Gary Smith and Sagantec President and CEO Hein van der Wildt across a beer on the final evening at DAC. And say you asked each of them to tell you something you didn't already know.
Gary would tell you that there are four well-known beverages that are a silent menace to those who would partake unawares – saki from Japan, grappa from Italy, anisette from France, and ouzo from Greece.
Hein, on the other hand, would still be in a DAC mode. He'd tell you that it's a relief that DAC is finally living up to its potential as a Trade Show – that for the first time ever this year, “trades” or “real business deals” were allowed to be transacted on the Exhibit Hall floor. He'd also tell you that DAC has moved another 10% of the way towards a true Euro-style show by allowing beer on the Exhibit Hall floor (on Micro-brew Monday). Hein said, “American companies are finally learning to take on a European lifestyle!”
If you combine these data points with the lament from 'foreign' companies who find it a tough go breaking into the American market, you might come to some sort of conclusion. Unfortunately between the beer, the saki, the grappa, and the wine – it's hard to know exactly what that conclusion is. Maybe Sir Robin or Alberto would know.
(Editor's Note: There's lots more to tell about DAC 2003. Coverage will continue in next week's newsletter.)