Editors, at least the ones who admit to being a bit unorganized at times, may occasionally fail to pay sufficient attention to a story that actually deserves closer scrutiny. The recent announcement of an alliance between Cadence and CoWare may be one of those stories. After listening in on a joint phone briefing from folks at Cadence and CoWare, and then unexpectedly receiving a phone call from the folks at VaST Systems Technology Corp. who wanted to point out the 'other side of the story,' I decided to sit up and take notice.
The Cadence/CoWare announcement is actually pretty interesting, principally because it's addressing a “new-ish” business model that may provide renewed enthusiasm for creative partnering across corporate firewalls within the EDA industry.
The Press Release (abridged):
Cadence Design Systems, Inc. and CoWare, Inc. announced a strategic alliance to accelerate time-to-market for SoC design teams through a standards-based system-to-silicon-design solution. This multifaceted relationship includes joint development, cross licensing, a coordinated go-to-market and standards strategy, and a Cadence equity investment in CoWare. The alliance provides a unified solution from electronic system-level (ESL) design through RTL implementation for advanced SoC designs and a new connection in the design chain.
Electronic design companies have long had separate system and IC design teams, each with their own unique development environment. With increasingly complex SoC designs, the gap between system and IC design environments has become a critical bottleneck.
CoWare and Cadence are seizing the opportunity created by the SystemC standard to provide a new level of design capability, speed, and efficiency. The first step is the creation of a system-to-silicon design solution based on CoWare's ConvergenSC and LISATek system-level design products and the Cadence Incisive functional verification platform. The allied companies are working with SoC design leaders such as ARM to ensure this unified flow is supported by interoperable IP.
The [Cadence/CoWare] alliance... leverages each company's technology and business strengths. It promotes the rapidly emerging transaction level of abstraction enabled by the SystemC standard system language, and provides the critical link for unifying the two worlds of system and IC design.
The two companies say they will coordinate their go-to-market activities, with CoWare focusing on the ESL design market, while Cadence focuses on the functional verification market. The companies' field sales and support teams will have shared goals and aligned interests in making joint customers successful.
As part of a special licensing agreement, the financial terms of which were not disclosed, Cadence has transferred to CoWare its Signal Processing Worksystem (SPW) group. The addition of SPW extends CoWare's ESL leadership by adding algorithm design to its processor, bus, SoC architecture, and hardware/software co-design tools. Cadence also has made an equity investment in CoWare.
Simon Segars, Executive Vice President for Engineering at ARM, said: “ARM is committed to working with its partners to develop and promote open technology solutions that accelerate platform-based design of advanced SoCs. Cadence and CoWare bring together leading system-level design and verification tools. Through our collaboration with them on SystemC models, more design teams will now be able explore ARM core-based designs earlier in the product cycle."
Sound bites from the major players:
Mitch Weaver is Vice President of Marketing for Functional Verification at Cadence, which includes the Incisive product line. Alan Naumann is President and CEO at CoWare. They spoke about the joint announcement in a conference call on Wednesday, September 10th.
Alan: “This is a very important announcement because of two things. First, system-level design has been growing in importance, but one principal technology has been missing - verification for designing at the system level. Designers didn't have a way to verify during implementation. This announcement is good, therefore, for early adopters and for mainstream users who are starting to use system-level design. CoWare's going to provide the system design solution for the Cadence customer base, so both companies have decided to take that part of the Cadence design business and move it over to CoWare, where there's a 100-percent focus on system-level design.”
“The second thing is that this is another move by both companies to support the two languages needed today - SystemC at the system level and Verilog plus extensions for implementation and verification.”
Mitch: “From the Cadence side, we're the market leader in functional verification. We introduced the Incisive Platform, bringing [to market] a forward-featured transaction-level verification environment tied to Verilog. The key element here was the standardization of SystemC, but that by itself is not sufficient to satisfy system-level design needs.”
“It's going to take a combination of CoWare's high-level transactional extraction, high performance, and flexible approach, combined with the Cadence tools to bring [the thing] all the way through to implementation. The Cadence/CoWare alliance provides a key element at the bridge between system-level and transactional-level performance to satisfy designs with multiple microprocessors in them that include embedded software and components from a variety of vendors. [As a result], it was also important to bring an IP provider like ARM into the agreement to make the component part.”
Alan: “I'm a strong advocate of really focusing on specific business and customer sets - that focus brings market leadership. This agreement allows Cadence to continue to focus on its five design platforms, while someone else solves the emerging system-level design problems. Cadence can have a partner who focuses on system-level design and customer benefits, without having to invest in that customer channel.”
“There is a second benefit for Cadence. SPW is an outstanding tool for engineers who want to design algorithms for media chips. The installed SPW customer base will be well served by transferring the technology over to CoWare for system-level design and algorithm design.”
Mitch: “So there's a couple of big pieces of news here. First, it's about bridging the transaction/system level and the other news is about a very unique relationship. I wouldn't call CoWare a startup, but the nature of system-level design is that it is for early adopters - the type of technology that is [pursued] at all costs in a start-up. The feature of this unique Cadence/CoWare relationship is to maintain what CoWare's good at. Our best engineers from Cadence will work with CoWare. The uniqueness of this [business] structure is the big news.”
“There have been two flavors of acquisitions over the last period of time. There have been broad acquisitions and integration of a company into a larger company. Verplex and Get2Chip were those type of mainstream technology acquisitions, not early adopter technologies, where Cadence integrated the company's engineers into our own R&D team.”
“The other flavor is this CoWare structure. [We see it as] the best way to serve the customers and to [preserve] the entrepreneurial nature of CoWare. It's very unique and the first of its kind. We're proud of our ability to bring it together.”
Alan: “It's true, traditionally there's been just two or three types of relationships in the industry. One involved acquisitions and the second involved market-level relationships that didn't make an impact. What we're doing takes something from both of these [types of relationships].”
“Cadence recognizes that normally they could assimilate a technology and deploy it for customers. But what we're doing here is for a different set of users. CoWare brings a unique system-level focus, different [from that] inside a normal EDA company. We're [attacking] different problems that require a different solution set.”
“Why doesn't a normal acquisition make sense here? Well, system designers are often in a different part of the corporate structure, and they speak a different language from RTL designers and layout engineers. When you talk about co-design, using MIPS or ARM, tweaking algorithms for instance for wideband CDMA, these are system decisions. Most EDA sales channels across the industry are not focused on that specific group.”
“Clearly, Cadence has been aggressive on acquisitions. However, Ray Bingham, Penny Herscher, and I all discussed what the right relationship should be here and it was clear to everyone that CoWare should remain an independent company. The larger EDA companies have put effort into system-level design, but nowhere near what CoWare has done in the management and R&D efforts. An acquisition by Cadence would have caused CoWare to lose focus.”
“This arrangement allows CoWare to remain independent and focus on this problem. It's a more difficult technical problem than even synthesis was 15 years ago. If we were part of another company, that effort would get diluted. In the long term, this is critical to the EDA industry and electronics. Without it, even EDA growth would be limited. Without innovation and people pushing the edge and solving customers' problems - from railroads to high-tech - innovators keep things moving ahead. After all, even Synopsys started as a little upstart and a thorn in the side of Daisy, Mentor, and Valid.”
“It's noteworthy, that Cadence and CoWare might be right or they might be wrong here, but we're definitely taking a different approach. How do both companies solve problems in a different way, while showing some innovation from a business point of view?”
“The Cadence engineers supporting SPW have been physically transferred and have become CoWare employees, similar to an acquisition. The team and the source code have moved over and now CoWare is supporting ongoing algorithm design. There will also be other tech support between the two companies. We'll be the key link between system design and verification. Meanwhile, the engineers will work at the Cadence site and at the CoWare site. There will be regular meetings to allow the two teams to stay in sync. There will be cross licensing to make sure that the design flow for customers works out of the box in a significant way. We'll make sure linkage exists.”
“[Clearly], there are extra precautions [in place] to determine who owns which IP and to protect confidentiality. These [arrangements] are artifacts of having more than just a marketing relationship. Cadence over the last 5 years has made it clear that it respects IP - especially other people's IP. We're fine with those assurances because we want this to be a success.”
Mitch: “[The legal] agreement is reasonably elaborate involving a go-to-market strategy, the operational nature and licensing issues [of the alliance], the transfer of people, plus the equity investment. At the end of the day, however, [we're comfortable] that it's all very tight and well defined. It's unique and meant to look like a single go-to-market product from these two collaborators, who are developing markets with a consistent, unified approach from a customer's perspective. We expect both CoWare and Cadence to have leverage with all of this. It's new technology, and the nature of the deal is such that the two companies don't have a lot of customer base overlap. There's an opportunity for acceleration for both of us here.”
Alan: “[This alliance] is something new and different. The biggest thing from CoWare's [point of view] is that now we're [playing] in a different league. CoWare will have more than 100 employees and over 3000 customers. We'll be the largest private EDA company out there, plus we'll have a great partnership with Cadence.”
“Will we be going public soon? It will be fun just to be the largest private EDA company for a while, although our plan is to build for the long term. The merger with LISATek earlier in the year, and this alliance with Cadence, has moved our [IPO] schedule out a bit. Now we want to have a bigger share of the industry. We believe, however, that within the next year and half - that's the time frame when our goals and the public equity markets will be ready [for an IPO]. [The timing] is a function of many variables.”
“Meanwhile, who's going to buy the champagne [to celebrate this new alliance with Cadence]? We think we can probably afford the champagne, but it won't be as fine a label as Cadence would probably buy.”
Mitch: “I think Cadence can probably afford the champagne.”
Alan: “I'm going to have to remind Mitch of that, the next time I see him in person.”
There are always two sides to every story:
Clearly, Cadence and CoWare think this is an important story. But VaST (and presumably others) think it's important as well, which is apparently why they sought to go on record with a rebuttal to the claims of the principals involved. Not surprisingly, the rebuttal was peppered with almost as many out-and-out marketing pitches as the Cadence/CoWare message.
Graham Hellestrand, President and CEO at VaST, told me, “The problem we see with the Cadence/ CoWare deal is that, to be successful in the system-level architecture and design space, you need very high performance software/hardware processor and platform modeling technology. You also need highly integrated tools and interfaces to industry leading software, such as MATLAB /Simulink, which dominates the signal processing market, and UML, which dominates software specification. Only VaST provides an integrated solution that meets this description.”
“We speak from a position of strength here. VaST's solutions provide the speed and accuracy necessary to serve the real-time embedded systems and EDA industries. Businesses such as automotive electronics, aerospace, cell phone, converged wireless LAN, and consumer electronics need integrated tools and high-performance, accurate models that enable them to implement efficient engineering processes for software-hardware system-level architecture and design. Everywhere there is real-time control using sophisticated microprocessor-based SOC designs, you have a need for this type of integrated solution set.”
Eventually, Graham got to the point of the call: “How the Cadence assets fit together with CoWare's design services business to create something that's useful to the customers is not clear. What we see in this deal is a mixed bag of tools and services, and that does not make a product offering. So the question for CoWare is, 'Where's the beef?'”
“We are aware that a Cadence/CoWare deal was in the making for a long time. We don't know CoWare's financial motivation, but can't see any end benefit to design engineers in this merger/ acquisition/ however-you-would-categorize-it. Customers will be committing millions of dollars to these designs, and, without high-performance models to protect their investments, I can't see how this deal will result in product offerings that will help them.”
At this point in our conversation, I asked Graham if, given the opportunity, VaST would decline or accept the opportunity to enter into a CoWare-type partnership with Cadence.
He answered, “You ask whether VaST would respond positively if Cadence were to come to us with a similar business proposition? We are business people interested in the success of our company. We would consider business proposals from anyone, including Cadence.”
That's probably sound thinking on the part of any CEO.
Industry news - Tools and IP
Cadence Design Systems, Inc. announced the shipment of its OrCAD 10.0 release, that the company says includes “new features, improved tool integration and enhanced technologies.” The OrCAD 10.0 release is intended to address specific design tasks of both PCB designers and electrical engineers by introducing three new OrCAD Unison design suite configurations - first, OrCAD Unison EE with OrCAD Capture for design entry and PSpice A/D for analog and mixed-signal simulation; second, OrCAD Unison PCB with OrCAD Capture for schematic referencing, OrCAD Layout for PCB place & route, and SPECCTRA for OrCAD autorouter; and third, OrCAD Unison Ultra for the entire design, from schematic entry
and simulation, to board layout and routing. The additional features included in all of this are complex, subtle, and worth a second look from existing and potential customers.
Denali Software, Inc. announced an agreement with HP to provide configurable memory controller cores and memory modeling solutions for the design and verification of chips used in HP's imaging and printing products. Denali Databahn memory controller cores are being used in HP chips to interface with double-data-rate (DDR) memory devices. The companies say the arrangement also provides HP with Denali's MMAV product for modeling and simulating the interactions between the HP chips and external memory devices for design verification and performance analysis.
Intellitech Corp. announced the availability of the NEBULA Silicon Debugger. The company says NEBULA reduces test-vector debug time from weeks to less than half a day through direct knowledge of on chip DFT (Design-for-Test) structures and integrated use of Synopsys TetraMAX ATPG patterns and diagnostics. NEBULA permits remote testing of prototype silicon for stuck-at faults, path-delay faults, at-speed BIST, and in-situ functional debug. Failures can be isolated to the gate and net level with access to the TetraMAX fault-simulation database for lookup of ATPG faults. The NEBULA acronym is “loosely translated” as Network Based debug and Logic Analysis - the debug and validation
platform is remotely accessible by design and test engineers over a wide area network. The tool understands the difference between serial scan test data and parallel pin test data, which allows engineers to debug using functional elements of the design rather than counting 'bits' from tester channel results. The company says that architecture and scripting language enables complex decision-making during execution of test programs that is not possible with memory-behind-pin tester architectures. The NEBULA platform also understands the DFT infrastructure inserted by Synopsys tools.
InTime Software, Inc. announced that Sony Corp. of Tokyo has adopted InTime's Time Planner for use in its SoC flow. Per the Press Release, Sony chose InTime because of its “unique RTL Timing Analysis software that provides fast and accurate RTL timing analysis and RTL floorplanning. Time Planner supports Sony's RTL handoff flow by providing accurate timing information on the RTL code before handing it off to the chip implementation flow.” Bob Smith, InTime's President and CEO, is quoted in the same Press Release: “Sony has been instrumental in helping prove out the value of using RTL timing analysis in a production flow. It is becoming clear that RTL timing analysis will play
an increasingly important role in the evolving IC design flow.”
Magma Design Automation Inc. announced that Toshiba Corp. and Toshiba Microelectronics used Magma software to successfully tape out and achieve first-pass silicon success on a 2.5-million-gate, low voltage (under 1.2V), low-power and high-speed consumer application device. The companies report that the complex SoC had 100+ clocks, including some running faster than 200 MHz. The chip was implemented utilizing Toshiba's TC280 (0.13-micron technology node) process and “Magma's integrated physical, hierarchical and signal integrity design technology.” The SoC included various operating modes, IP including ROM, RAM, and tricky interfaces, yet according to the companies was
implemented in just four weeks using the Magma tools.
Also from Magma - The company announced that Applied Micro Circuits Corp. (AMCC) taped out a 622 MHz design with 3.4 million “placeable objects” using Blast Fusion, Blast Noise, Blast Plan, and Blast Rail. The company also reports it received AMCC's "Supplier of the Year" and "Innovation Award" commendations for “helping AMCC bring products to market in a timely and cost-effective manner.”
Mentor Graphics Corp. and Verisity Ltd. announced a technology collaboration that will allow customers to test Mentor Graphics Inventra IP functionality and help ensure smooth integration of an IP core into a target design. Mentor Graphics says it is joining Verisity's Pure IP program and can now deliver verification toolkits based on Verisity's Specman Elite automated functional verification methodology for its IP. The verification toolkit includes executable checkers and coverage scenarios that ensure correct IP integration. The toolkits act as an invisible wrapper around the IP, allowing customers to automatically check for adherence to the rules and flag incorrect usage as well as measure the coverage of the IP interface.
Michael Kaskowitz, General Manager of Mentor's IP Division, said: “Customers are pushing for sophisticated verification components that ease the dual problems of performing comprehensive functional validation of an IP block and also providing capabilities to migrate to pre-silicon, SoC, system-level testing. The Pure IP program will help us deliver flexible verification toolkits to our customers."
Also from Mentor - The company announced design-for-test (DFT) support for the AMD Opteron processor and AMD64 architecture. Mentor says it will offer AMD64 versions of its embedded deterministic test (EDT) tool, TestKompress, and its automatic test pattern generation (ATPG) tool suite. Robert Hum, Vice President and General Manager of the Design Verification and Test Division at Mentor, is quoted in the Press Release: “Our DFT products have been available on Linux for some time and we planned our 64-bit rollout to coincide with the growing industry need. The flexibility and scalability of the AMD64 architecture complements the flexibility and scalability of our tools and offers customers a comprehensive solution for their next generation designs."
One last item from Mentor - The company announced that it has selected Paradigm Works to aid in the development of system-level verification toolkits that Mentor will deliver with its Inventra IP. Paradigm Works says it offers an advanced verification component technology that ensures that customers can rapidly integrate their devices based on Mentor cores and thoroughly validate the quality of the integration.
Per the Press Release, verification is one of the most critical parts of the SoC development process. With ever-increasing mask costs, it is critically important to be assured that a design is functional before tape-out. The semiconductor industry is moving to the use of sophisticated verification components to facilitate SoC functional verification - especially as typical designs now carry multiple interfaces using different complex, communication protocols. This presents a challenge to designers, as verification environments must move vertically from the IP level to the chip level, so that the interaction between all sub-systems can be verified to a high degree of confidence.
Dave Wood, Director of Marketing for the IP division of Mentor Graphics, is quoted: “Increasing IP complexity requires a layered approach to verification to provide SoC designers with early feedback on potential system-level problems. Paradigm Works helps Mentor Graphics extend verification to the system level by providing a feature rich verification component to improve the functional quality of our customers' designs, and help achieve first pass success.”
MLDesign Technologies today announced the availability of a new MLDesigner evaluation CDROM that can be used with Windows computers. The new CDROM temporarily installs a temporary Linux operating system on a Windows computer and then loads MLDesigner for use. While in operation, MLDesigner accesses Linux files from the CDROM. After the evaluation, MLDesigner and all Linux files are removed from the host computer. Currently, MLDesigner runs on Solaris and Linux; a Windows version is in development. The evaluation CD contains a complete functional version of MLDesigner, including Discrete Event, Data Flow and Continuous Time design domains, a library of 2000+ design blocks, 400 demonstration systems, and documentation.
Synopsys, Inc. announced that Agere Systems used Synopsys' Galaxy Design Platform, including Physical Compiler, Astro, Star-RCXT, and Jupiter to tape out the 5G APP550 network processor in a 0.13-micron process. Agere says its ASIC design flow is built around Physical Compiler and that company engineers used Physical Compiler's synthesis and placement together to obtain a “timing-clean result in a short and predictable time.” The APP550 network processor was designed using Agere's SoC design flow, which centers on Astro for physical implementation. The companies say that the tight integration between Physical Compiler and Astro's signal integrity-aware routing allowed Agere to complete the network processor on-schedule and produce parts working to specification.
Also from Synopsys - The company announced that NEC Electronics Corp. has adopted Star-RCXT for its 90-nanometer CB-90 design flow. NEC and Synopsys say the companies collaborated to improve Star-RCXT's advanced interconnection modeling technology for CB-90's fine copper process features, which includes spacing, width and metal density-dependent wire resistance and capacitance calculation. The companies also say that Star-RCXT's support for advanced copper features “enables NEC Electronics to meet timing and signal integrity sign-off accuracy goals for designs using their 90-nanometer process.” Meanwhile, NEC says it Electronics' CB-90 ASIC design platform utilizes “its most
advanced system LSI process technology, supporting clock speeds up to 1 GHz and featuring up to 100 million usable gates.” That's a helluva lot of gates.
Synplicity Inc. announced its FPGA logic synthesis and physical synthesis products now provide support for the Xilinx Integrated Software Environment 6.1i (ISE). The companies say that Synplicity's Synplify and Synplify Pro FPGA synthesis software can work directly with Xilinx's ISE 6.1i software. The Press Release says, ”Customers using Synplicity's Synplify logic synthesis and Amplify FPGA physical synthesis products together with ISE 6.1i will have access to a complete FPGA design solution for their high-speed designs.”
Not surprisingly, both companies feel the announcement to be mutually beneficial. Jeff Garrison, Director of FPGA products at Synplicity is quoted: “Leading edge devices like Spartan-3 and Virtex-II Pro from Xilinx have opened up significant new opportunities in electronic applications for programmable logic. These applications require advanced design software like Synplify Pro, Amplify and ISE 6.1i to get the most out of the silicon.”
Steve Lass, Director of Software Product Marketing at Xilinx is quoted: “Through our continued partnership [with Synplicity], we are providing designers with comprehensive design flows from synthesis to place and route. These design solutions, coupled with Xilinx's flagship Virtex-II Pro Platform and 90nm/300 mm Spartan-3 low-cost FPGAs, create the highest performance, most cost-effective hardware/software solution available in logic design today.”
Similarly - Mentor Graphics Corp. announced a collaboration with Xilinx, Inc. to provide “seamless operation between its FPGA Advantage design environment and Xilinx's recently announced Integrated Software Environment 6.1i (ISE).”
The companies say that FPGA Advantage, integrated with Xilinx's new ISE 6.1i tools, delivers a complete FPGA flow that redefines the standard for productivity in programmable logic design software. Both Mentor and Xilinx say they “are committed to providing the most complete, intuitive design solution available for FPGA design.”
Proving that lightning strikes twice, the Press Release also says: “The enhanced FPGA design flow includes hardware and software design creation and verification environments with synthesis, design management, timing analysis and place and route capabilities. This design suite, coupled with Xilinx flagship Virtex-II Pro Platform FPGAs and 90nm/300mm Spartan-3(TM) low-cost FPGAs, creates the most cost-effective hardware/software solution available in logic design today.”
Finally - Hier Design Inc. announced that its PlanAhead hierarchical floorplanning and analysis software now offers support for the latest version of the Xilinx Integrated Software Environment 6.1i (ISE).
The companies say that the combination of ISE 6.1i and the PlanAhead software gives users of Xilinx Virtex-II and Spartan-3 device families an ASIC-like flow for the design of FPGAs. Customers benefit from a proven methodology for reducing place and route time, the number of design iterations, and the time needed to achieve timing requirements. Jerry Banks, director of Global Alliances at Xilinx, is quoted in the Press Release: “Hier Design's PlanAhead software provides a unique FPGA design solution, which will help enable the further growth of the FPGA market. Our development groups have worked closely together to ensure the tightest possible integration and to deliver a design flow with unmatched high-speed design capabilities and ease-of-use floorplanning features."
Newsmakers
New voices in EDA - Last week, Carbon Design Systems announced itself to the EDA community, along with products for system validation of hardware/software “in an enterprise-wide environment.” This week, I had a chance to get some feedback from senior management of the new company - Stephen Butler, President and CEO, and Kevin
Hotaling, Founder and Vice President of Worldwide Sales. Not surprisingly, they're pretty jazzed about the company and life in general.
Kevin said, “I was at Quickturn for 10 years, [where I had] first-hand experience with the value of getting to software early. The problem was to deploy to a broader audience, to get the design out to the users more quickly. Our founder and CTO [here at Carbon], Bill Neifert, developed algorithms for accelerating Verilog RTL, a vector of need in the marketplace and more than what was being delivered by EDA. He took it to the VCs at the end of 2001, had good traction, and closed the first round in June 2002 with $5 million.”
“At Carbon, we're focused on the validation market. Everybody validates, but most people do it by building silicon. [By contrast], we're doing pre-silicon systems validation, which represents a $2 billion market. Few use EDA tools to do this work, most use emulators - which adds an additional $3 billion on top, representing the costs of labor and equipment. Some people build custom models, cycle-accurate models, hoping to get something to the software developers early on. Even more people build FPGA breadboards - a $1 billion market for pre-silicon validation. But the focus for us is an early firmware diagnostic. We have the capability to deliver a golden RTL model.”
Steve then had a turn: “I was running a public company, Segue Software, which is an enterprise software company. It had turned nicely profitable and I was pretty happy there. Then Kevin came calling - I knew Kevin from the late 1980's at Quickturn - and I started to look at Carbon and was excited about the EDA-to-enterprise kind of story I saw there. I also looked at what I like about EDA - high value sales, very strategic - and what I don't like about EDA - it's a small market.”
“I had left EDA and gone into enterprise software, because it was bigger. What I have not liked about enterprise software, however, is the rapid commercialization of the tools. It requires a kind of monopoly to get any sort of margins in that industry. EDA, however, has high value and crosses over into the enterprise - dealing with customer's engineering and software teams. I got the picture with Carbon that this is 'EDA to the enterprise.' Our idea is catching on fast, the product is meeting all expectations, and we've even had revenue, which we hadn't expected to realize until late next year. A lot of portfolio companies have no revenue or miss their goals. We're just the opposite.”
“Carbon's an interesting company. It's founded by someone with an executive sales background and someone who comes out of the application space. Usually, you would need an engineer to build a prototype to get money. But it's been different here. This product has really been thought out with feedback from customers. Kevin has worked with 20 different customers and knows exactly what the problems are. Then he brought in the engineering team to build to the customers' requirements.”
Kevin emphasized that this is the perfect time to be starting out: “One of the most exciting things [about building a company] in a down economy is the ability to assemble the kind of Dream Team we've got here at Carbon. [They come with a wealth of experience], some bounced out by the downturn, some available through the end of the dot.com bubble. It's been a great opportunity for us.”
Steve was even more adamant: “There have been absolutely no disappointments since I came over to Carbon in spring of this year. I'm just loving it.”
Good times.
Cadence Design Systems, Inc. announced that Business 2.0 has named Cadence as one of the fastest-growing technology companies in their second annual B2 100 ranking. Cadence ranked 84 on the list. Criteria for making the final list included at least 3 years of trading on a major U.S. stock exchange, at least $50 million in annual revenue, and positive cash flow over the most recently reported 12 months. Business 2.0 editors then ranked the companies with the help of Zacks Investment Research of Chicago, using a combination of four criteria: growth in revenue, profit, operating cash flow during the past three years, and the 12-month stock return. Cash flow growth counted for 40 percent of a company's ranking; each of the other criteria counted for 20 percent.
QualCore Logic Inc. (founded in 1994) announced it has acquired LEDA Systems Inc. (founded in 1995) of Plano, TX, a leading provider of analog and mixed-signal silicon IP. The companies say the acquisition expands QualCore Logic's portfolio of digital IP and design services to include a full complement of mixed-signal, analog and radio frequency (RF) offerings, and enables QualCore Logic to fully support various markets with a range of silicon IP, design services, and full-service ASIC capabilities. Financial terms of the acquisition are not being disclosed. The combined company has offices in Sunnyvale, CA, Plano, TX, and Hyderabad, India, and now has close to 200 employees
and consultants.
Sequence Design says it is opening the New Delhi Center of Excellence, its fifth, to provide R&D and marketing resources for Sequence worldwide, as well as post-sales support for customers in India and nearby regions. The company's other Centers of Excellence are in Acton, MA, Austin, TX, Santa Clara, CA, and Tokyo, Japan. Sequence says it plans to invest as much as $2 million over the next 12 months in its India operations. Sequence India's General Manager is Krishna Kumar, who has 15+ years' experience in the industry, including senior positions with Mentor Graphics, IBM, CrossCheck, and DRDO. Sequence India will initially employ 30 engineers, with plans to double that number by 2005.
SynTest Technologies announced that they have signed Logicad Technologies to be SynTest's distribution partner for India. The company says that many semiconductor multinational corporations, large IDMs, and small fabless semiconductor companies are either setting up their own design centers in India or offering turn-key projects to Indian design companies, which has generated a growing need to provide EDA tools and even DFT technology locally in India. Ravi Apte, Vice President of Strategy and Business Development at SynTest, is quoted in the Press Release: "The emerging market for ASIC design in India calls for timely local EDA and DFT support. We are happy to be working with
Logicad, with its ideal credentials, to help provide local support in India to companies seeking to improve their ASIC and system testability and reduce test costs.”
Meanwhile, Logicad says it has roots in both Silicon Valley and India. Shiv Turmari, Senior Deputy General Manager of Logicad India, is quoted: “Logicad has already tied up with renowned EDA tool vendors as their exclusive distributors to India. We have made a thorough study of the Indian DFT market. With the present market scenario and improved economy, we are happy to tie up with SynTest, one of the major DFT tool vendors.”
Verisity Ltd. announced the expansion of its University Program with 22 new university members. The total number of participating academic institutions is now 45. The twenty new member universities are: Alfred University, Arizona State University, University of Bristol, Darmstadt University, Kyoto University, Loughborough University, Massachusetts University, Nebraska-Lincoln University, Northwestern Polytechnic University, Ohio
State University, Osaka University, Purdue University, Santa Clara University, Swiss Federal Institute of Technology (EPFL), Texas A&M University, University of Texas at Austin, The University of Arizona, University of California at Irvine, University of California at Berkeley, University of California at Davis, Washington State University, and Washington University.
Prof. Mulvaney of Loughborough University in the U.K. is quoted in the Press Release: “Experience with industry-standard tools enhances their employability and ensures our program remains attractive to new students. We value highly the partnership between Verisity and Loughborough that has been established by the University Program."
In the category of...
The sands of time
The PBS/Ric Burns documentary on the WTC ran for the better part of 3 hours this past Monday night. Long as it was, from beginning to end it was a gripping piece of journalism. I was at the WTC site myself 10 days ago, which was an even more gripping experience. It was cold, gray, and drizzling, but people were there nonetheless - many curious, but most like pilgrims visiting a shrine, a crowd of quiet and courteous people looking through the cyclone fencing and grappling with something that was beyond comprehension.
Now it's Thursday, September 11th, and for those on the West Coast who wanted to see memorial services broadcast live from the East Coast - from New York, Pennsylvania, and Washington, D.C. - it was possible to tune in at 5:30 AM and spend 3 additional hours in front of the television before the workday began.
At this point, so many things have been said, so many words have been written, so many events have transpired as a result of that Tuesday morning two years ago - politically, economically, militarily, socially - it's hard to grasp it all, no matter how many hours are spent in front of the television or standing at the edge of the WTC pit.
During the PBS documentary, someone commented that life in New York City is back up and running full tilt once again, healing over the wounds like the waves at the sea shore inevitably smooth and restore 'wounds' in the sand at the water's edge. Wounds in people's lives can be healed over. Life can go on. It's not a matter of disrespect to the dead, it's a matter of respect for the living. People can't live as if there is no tomorrow. The greatest healing comes with simple acts of life returning to normal.
I'm going to dwell on that thought for today. I'm going to take a quiet walk and enjoy a sunny day. Tomorrow is soon enough to pick up the front page once again and wring my hands, along with the rest of the world, over the ongoing saga of human frailty, hate, and revenge.