Averant Announces Release of SolidAC(TM) 3.0
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Averant Announces Release of SolidAC(TM) 3.0

HAYWARD, Calif.—(BUSINESS WIRE)—May 22, 2008— Averant Inc., a leading provider of advanced verification technology for RTL designs, today announces the release of SolidAC 3.0, continuing its First In Formal leadership in formal property verification. SolidAC is a subset of Solidify, containing a module browser, RTL compilers, source code debugger and waveform display, and a set of automatic checks such as dead code, deadlock, livelock, clock crossing, constant signals, FSM checks, X propagation issues, array over-bound, reset, tri-state buses, and pragma. In addition to including a set of bug fixes, the key new features of this release are:

SolidAC 3.0, with its ease-of-use, modern GUI, and attractive pricing, enables formal verification to reach a much wider audience, commented Carey Sayer, president of Saros, Averants distributor in the UK. With virtually no training, designers can use SolidAC to find a variety of issues early on so that verification can proceed more smoothly. I believe no design house can afford not to have a version of SolidAC in-house.

Availability

Solidify 3.0 is available on Windows, Linux and Solaris platform.

About Averant

Averant Inc., founded in 1997, is a privately held EDA firm pioneering new methodology and technologies for static formal verification. Averants flagship product is Solidify, a robust formal verification engine that provides the basis for property-based design verification, protocol verification, timing constraint verification, and automatic design checks all without the need for simulators or test vectors. These tools are easily adopted into the design flow, and help improve quality, reduce risk, and speed the design process. For more information, see our web site at http://www.averant.com.



Contact:

Averant Inc.
Ramin Hojati, +1-510-581-8881 x320
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