Integration of PureSpec and AVM Ensures Availability of High-Quality Verification IP for Advanced SystemVerilog Verification
"Mentor and Denali have enjoyed a close working relationship and have addressed common customer interoperability requirements with tight integrations between our Questa Platform products and Denali's memory models and verification IP products," said Robert Hum, vice president and general manager of Mentor Graphic Design Verification and Test division. "This integration with our AVM libraries builds on that relationship to provide our customers the most powerful verification environment to achieve increased productivity and quality."
"The industry is now clearly embracing SystemVerilog for functional verification," said Mark Gogolewski, chief technology officer for Denali Software. "The availability of proven commercial tools and methodologies, like Questa and AVM, offer a significant incentive for the industry to adopt this technology and we see this happening today. By ensuring an optimal integration between our PureSpec verification IP products and Mentor's AVM libraries, we enable customers to leverage all the benefits that SystemVerilog has to offer for functional verification."
About the AVM
Announced in May 2006, the Mentor Graphics AVM is the first true system- level-to-RTL verification methodology, integrating advanced verification techniques like constrained-random stimulus, functional coverage and assertions into a single transaction level modeling (TLM)-based framework implemented in both SystemC and SystemVerilog. The AVM open-source library features an object-oriented coding style to reduce the amount of testbench code and a modular architecture to enable reuse. The AVM consists of the AVM Cookbook, a "how-to" guide for getting started, and source code for base class libraries, utilities, and implementation examples written in both SystemC and SystemVerilog. To access the Mentor Graphics AVM visit: http://www.mentor.com/go/cookbook
About PureSpec Verification IP
PureSpec is the most widely used Verification IP product used for functional verification of complex chip designs. PureSpec provides the most complete solution for validating compliance and interoperability of key interfaces, including ASI, AMBA, CE-ATA, Ethernet, PCI Express, PLB, Serial ATA, USB 2.0/OTG, and all DRAM and flash devices. The products include configurable bus functional models (BFMs), protocol monitors, and complete assertion libraries for all components in the interface specification. Quality, completeness and seamless integration with all modern verification environments, including Mentor AVM, make PureSpec the solution of choice for functional verification and interoperability validation for key SoC interfaces.
About Denali Software
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to- market for electronic system and chip design. Denali is headquartered in Palo Alto, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at http://www.denali.com.
Denali, Denali Software, and PureSpec are registered trademarks of Denali Software, Inc. Mentor Graphics is a registered trademark, and Questa is a trademark of Mentor Graphics Corporation. All other trademarks are property of their respective owners.
Pierre Golde
Denali Software, Inc.
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