What: Tensilica(R), Inc. will participate in artistic creations
for charity, book signings, panels and technical
presentations at the 43rd Annual Design Automation
Conference (DAC) held June 24 - 27, 2006, in San Francisco.
Monday, June 24 - Thursday, June 27:
Exhibit Hall Hours
Painting Murals to Support the San Jose Ballet
Tensilica Booth #3548 (North Hall)
By painting 10"x10" canvases, conference attendees
will artistically contribute to giant murals, designed
by German artist Lothar Krebs, that will be given to
leading Silicon Valley companies that make substantial
donations to Ballet San Jose. Ballerinas from Ballet
San Jose will be assisting the artists in the
Tensilica booth. Attendees will be able to paint part
of a different technology-themed picture each day.
Monday, June 24:
4:15 - 5:15 p.m.
Book Signing for:
-- "Designing SOCs with Configured Cores: Unleashing the
Tensilica Diamond Cores Technology"
-- Written by Steve Leibson, Tensilica Technology
Evangelist
-- "EDA Handbook"
-- Edited by Grant Martin, Tensilica Chief Scientist
Booth 2228 (South Hall)
Books will be available for sale and attendees are
invited to meet and have copies signed by Steve
Leibson and Grant Martin.
Tuesday, July 25:
11:30 a.m. - 2:00 p.m.
SystemVerilog User Forum Luncheon -- "SystemVerilog for
Integrating IP"
Akilesh Parameswar, Hardware Engineer, presenter
San Francisco Marriott Hotel, Salons 10-15, 55 Fourth
Street, San Francisco, CA 94103
The use of IEEE Std. 1800-2005 SystemVerilog to
increase design and verification productivity and
quality is growing rapidly. Presenters will discuss
the benefits and pitfalls of using SystemVerilog, a
unified design and verification language.
Tuesday, July 25:
12:00 - 2:00 p.m.
4th Annual DAC ESL Technology Symposium -- "Putting ESL to
Work: Successful IP Selection, Integration and
Interoperability for Effective SoC Design"
Grant Martin, Tensilica Chief Scientist, presenter
Room 200
This symposium will discuss how IP and EDA companies
are using ESL to cope with the increasing complexity
and scheduling demands of SoC design with new tools,
techniques and methodologies.
Wednesday, July 26:
8:30 a.m. - 12:00 p.m.
MPSoC Design Tools Session: "Overview of the MPSoC Design
Challenge"
Grant Martin, Tensilica Chief Scientist, presenter
Room 306-308
Presenters will show how software design tools can
help alleviate problems, what parts of the design flow
can be fully automated, and what parts can be assisted
by design tools. Grant Martin will present a paper
titled, "Overview of the MPSoC Design Challenge."
Thursday, July 27:
12:00 - 12:45 p.m.
Troubleshooting the Multi-Processor SoC Design Flow
Grant Martin, Tensilica Chief Scientist, presenter
Pavilion Panel
This panel will discuss how the hardware and software
worlds can unite to conquer the complex
multi-processor SoC design problem.
Where: Tensilica Booth #3548 North Hall
Design Automation Conference
Moscone Convention Center
San Francisco, California
Who: Tensilica offers the broadest line of controller, CPU and
specialty DSP processors on the market today, in both an
off-the-shelf format via the Diamond Standard Series cores
and with full designer configurability with the Xtensa
processor family. Tensilica's low-power, benchmark proven
processors have been designed into high-volume products at
industry leaders in the digital consumer, networking and
telecommunications markets. All Tensilica processor cores
are complete with a matching software development tool
environment, portfolio of system simulation models, and
hardware implementation tool support. For more information
on Tensilica's patented approach to the creation of
application-specific building blocks for SoC design, visit
www.tensilica.com.
Editors' Notes:
-- Tensilica and Xtensa are registered trademarks belonging to Tensilica Inc. All other company and product names are trademarks and/or registered trademarks of their respective owners.
-- Tensilica's announced licensees include ALPS, AMCC (JNI Corporation), Aquantia, Astute Networks, Atheros, ATI, Avago Technologies, Avision, Bay Microsystems, Berkeley Wireless Research Center, Broadcom, Cisco Systems, Conexant Systems, Cypress, Crimson Microsystems, ETRI, FUJIFILM Microdevices, Fujitsu Ltd., Hudson Soft, Hughes Network Systems, Ikanos Communications, LG Electronics, Lucid Information Technology, Marvell, MediaWorks, NEC Laboratories America, NEC Corporation, NetEffect, Neterion, Nippon Telephone and Telegraph (NTT), NVIDIA, Olympus Optical Co. Ltd., Pnp Network Technologies, sci-worx, Seiko Epson, Solid State Systems, Sony, STMicroelectronics, Stretch, TranSwitch Corporation, u-Nav Microelectronics, Victor Company of Japan (JVC) and WiQuest Communications.
Contact:
Tanis Communications Erika Powelson, 831-424-1811 Email Contact