Aldec Design and Verification 
Radek Nawrot
Radek is a software product manager at Aldec, responsible for Active-HDL and Riviera-PRO product lines. He has over 7 years of experience in design and verification, including his role in the R&D division of Aldec in Europe. Radek hold his M.S. in Electronic and Communication Engineering from … More » FPGA VHDL Verification – Can we do this faster – with better quality – at no extra cost?November 14th, 2016 by Radek Nawrot
As I recently shared, UVVM, VHDL’s long-awaited alternative to UVM, promises to be interesting. Later this week, I’ll be joined by Espen Tallaksen, Bitvis Managing Director and Founder for a joint webinar, UVVM – A game changer for FPGA VHDL Verification. Below, please find Espen Tallaksen’s recent guest blog on the topic that originally appeared on the Aldec Blog. FPGA VHDL Verification This is actually possible – and with an average efficiency improvement of 20 to 50% for medium to high complexity FPGAs. Less for data path oriented designs and more for control or protocol oriented designs. At no extra cost. All that is required is that you do your testbench development the same way you do your design. Every single FPGA designer knows that a good top level design architecture is critical. Most FPGA designers also know that a good microarchitecture is at least as important for module design. It should thus be obvious that a good architecture is also equally important for your testbench, but for some strange reason most testbenches do not have the same good architecture as the design being verified. Most designers agree that the following are critical for an efficient development of a high quality design module: – Overview, Readability, Simplicity – Modifiability, Maintainability, Extendibility – Debuggability – Reusability So why should testbenches be any different, with on average the same time usage as the actual design?
It should be obvious that these aspects are equally critical for testbench development, but there has been no standard solution to build a good testbench architecture – until now – when UVVM has been introduced as a free and open source solution to this challenge. UVVM basically mirrors the design structure with verification components to handle each interface (or design module) and an easily understandable – yet powerful command structure to control and synchronize the verification components.
Most HW, FPGA and SW designers will understand the block diagram shown in the figure, and they will also easily understand the commands from the test case sequencer to control the verification commands. This is basically UVVM in a nutshell; – A very structured architecture and commands that allows almost anyone to easily apply stimuli on and check outputs from the DUT (Design Under Test) – even for a high number of simultaneously active interfaces. UVVM thus handles all the critical aspects listed above – in a very structured manner, and is really gaining momentum now. You can hear more about the challenges, the solutions and the benefits in the upcoming webinar to be jointly presented byBitvis and Aldec, UVVM – A game changer for FPGA VHDL Verification. The live event will be offered at two times on Thursday, November 17. You can register for a time that’s convenient for you in the US or Europe.
Tags: Active-HDL, debuggability, extendibility, fpga designers, fpga vhdl verification, hw designers, maintainability, modifiability, overview, readability, reusability, Riviera-PRO, simplicity, sw designers, testbenches, uvvm Categories: ALINT-PRO™, FPGA Design Creation and Simulation, Functional Verification |
|
|
|
||||||
|
|||||||
|
|||||||
