Custom Layout Insights 
Graham Etchells, Director of Product Marketing at Synopsys
Graham Etchells started in EDA before it was termed EDA. He has held marketing and sales positions at several companies and has been chasing the holy grail of analog/custom layout automation ever since he was a marketing director at Cadence in the mid-1990s. He says past experience indicates we may … More » Hurricane FinFET (Part 1)February 24th, 2016 by Graham Etchells, Director of Product Marketing at Synopsys
In my last post, I said: “A hurricane has made landfall and its name is FinFET”. OK, it’s a little corny, but it was not meant to convey a sense of impending doom for custom layout productivity. No question that hurricanes are disruptive, but humans can adapt to even the worst nature can bring. And FinFETs bring tremendous benefits along with the disruption.FinFETs are without doubt the most radical shift in semiconductor technology in decades, but moving to FinFETs is absolutely necessary. As feature sizes became finer, high leakage current due to short-channel effects threatened to put the brakes on scaling. FinFETs address the leakage issue and give Moore’s Law a new lease of life.Today the bulk of design starts are at the established nodes above 28 nm, so not everyone doing custom layout has experience with FinFETs. For those who have not yet felt the ‘winds of change’ that FinFETs bring, here is a brief primer.
FinFETs are not new; they have their technology roots in the 1990s, when DARPA looked to fund research into possible successors to the planar transistor. A UC Berkeley team led by Dr. Chenming Hu proposed a new structure for the transistor that would reduce leakage current. The Berkeley team suggested that a thin-body MOSFET structure would control short-channel effects and suppress leakage by keeping the gate capacitance in closer proximity to the whole of the channel.
Planar MOSFET and FinFET transistors As shown in the diagram above, modern FinFETs are 3D structures that rise above the planar substrate, giving them more volume than a planar gate for the same planar area. The gate “wraps” around the channel, so very little current is allowed to leak through the body when the device is in the off state. This allows the use of lower-threshold voltages, which results in optimal switching speeds and power. In addition, the agonizing trade-off of performance vs. power that designers continually face is also addressed by the FinFET. Now designers can choose to run the transistors faster and use the same amount of power, compared to the planar equivalent, or run them at the same performance using less power. This enables design teams to balance throughput, performance and power to match the needs of each application. So, have we reached Nirvana? Are FinFETs the designer’s dream? Well, there are some gotchas, especially when it comes to layout. But that’s another post… Tags: 3D, custom design, EDA, FinFET, layout, Moore's Law, MOSFET, planar, SoC, Synopsys, UC Berkeley |
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