If you’re a designer looking for a rare opportunity to shine, look no further. The folks at Erfurt-based X-FAB and Silicon Valley-based efabless hope to “further ingenuity” by extending a challenge to anyone in the world willing to accept it.

What they’re looking for are IP designs applicable to an ultra-low power voltage reference, and the companies are willing to make it worth your while.

If your design is one of the top three selected, you’ll receive a monetary award and your IP will be made available to a global customer base through both X-FAB’s IP web portal and efabless’ online marketplace.

Best of all – you’ll hold onto all rights for your submission.

Hello again!

In the last blog post I profiled the use of Custom Compiler’s Symbolic Editor for rapid digital cell layout.

In this post, we will tackle analog cell layout and show some more of the Symbolic Editor features that enable analog layout engineers to complete their layout in minutes vs. hours.

As with the digital cell layout, engineers can take advantage of the Symbolic Editor’s ability to define multiple P and N row pairs, as shown in Figure 1.

Figure 1. Multiple Row Pairs

The preview window shows how the layout will look when realized on the layout canvas. In this example, it is clear that in order to make the design more compact, the larger transistors need to be folded.

Folding the transistors is very easy using the Symbolic Editor. Options on the toolbar allow the designer to fold the transistor by specifying either the number of segments desired or by specifying a width threshold. Once the option is set, all the layout engineer has to do is simply select the appropriate devices and have them folded such that the transistors fit neatly in the rows. Figure 2 shows how the design looks before and after folding.