We’re only a few short days away from unveiling the EDA Consortium’s new name, new look and expanded mission to move us into the future. Based on the RSVPs, we’re expecting a huge crowd at our launch party Wednesday, March 30, that will feature wine and craft beer tasting and hors d’oeuvres. Don’t miss out on this stellar networking opportunity –– we have some of the industry’s top leaders coming.
Yes, the evening is meant to be a social gathering to celebrate the future of the Semiconductor design ecosystem, the critical driver of the worldwide semiconductor and electronic products markets. We’ll toast our storied past as well. I’ll interrupt the festivities with a short presentation on the new EDAC and will take the wraps off our new name and new look.
It’s not too late to register to join us. Everyone is welcome. The evening, open free of charge, starts at 6:30 p.m. and will run until 8:30 p.m. at the EDA Consortium/SEMI Global Headquarters, 3081 Zanker Road in San Jose, Calif. For registration details, go to: http://goo.gl/VBrezS
We look forward to seeing you and sharing our vision.
To speak with Herb Reiter about the rationale for multi-die packaging is a chance to follow a logical and energetic continuum from first principles to a final conclusion. Namely, that as the era of the ASIC subsides, the era of the multi-die package will arrive full force.
Reiter, President of eda 2 asic, will be reiterating this line of thinking, in conjunction with a panel of like-minded experts, at the upcoming EDPS conference in Monterey on April 21st. In anticipation of that session – “Multi-Die IC Design and Application” – we spoke by phone this week. The conversation was compelling.
Luckily, there wasn’t time this week to speak by phone with Mentor Graphics CEO Wally Rhines. After all, who wants to hear bad news in person: EDA has turned south.
Here’s the quote from Rhines included in EDAC’s press release discussing their Market Statistics Service report for Q4_2015:
“After 23 consecutive quarters of growth, the EDA Industry revenues declined slightly in the fourth quarter, compared to a particularly strong Q4 2014. However, industry revenue increased 5 percent for calendar 2015 compared to 2014, and the semiconductor IP and services categories increased in Q4. Geographically, the Asia Pacific region continues to grow, while other regions saw modest declines this quarter.”
Last week, we used an update on the Accellera Portable Stimulus Working Group (PSWG) presented at the Design and Verification Conference and Exhibition (DVCon) as a jumping-off point to discuss the status of this standardization effort and some key aspects of the three proposals currently under consideration. We were not the only blog to cover portable stimulus topics from DVCon; Brian Bailey of SemiconductorEngineering and Bernard Murphy from SemiWiki also posted their observations.
Earlier this week, EDACafe blogger colleague Peggy Aycinena posted a thought-provoking look at PSWG and the portable stimulus challenge. In regards to the scope of the proposed standard, she noted “a distinct wow factor in all of this, it’s so comprehensive” and said “this whole effort seems massive to me.” Today we’d like to respond to Peggy’s comments and questions, noting both the challenges of a portable stimulus standard and the availability of a working solution today.
In December 2015, Oski challenged formal users to build the fastest testbench to solve our Oski Formal Puzzler – the Chessboard Challenge, Berkeley Math Circle Monthly Contest 8, 2011, proposed and designed by Evan O’Dorney, three-time Putnam Fellow. Jesse Bingham from Intel submitted the winning entry, as was announced during a presentation at the recent meeting of the Decoding Formal Club in Santa Clara, CA on February 29, 2016. This was an opportunity to promote the adoption of formal verification across the semiconductor industry, and share formal techniques by showing how they might be used to solve a fun formal puzzle.
As customary, the 2016 DVCon/San Jose was held at the DoubleTree Hotel. The dates this year were February 29-March 3.
Attended by approximately 1,200 visitors (about 700 paying customers and 400+ on the free day) and 30 exhibitors, its program included 12 tutorials, 13 technical papers and 45 posters. Topics were on various aspects of design and design verification, with particular emphasis on hardware emulation, Universal Verification Methodology (UVM), portable stimulus, low-power design, and formal.
The event offered a keynote, two panels, one roundtable and three sponsored lunches by each of the three main EDA giants. A conversation between Jim Hogan and Ajoy Bose titled “Crossing the Chasm: From technology to Valuable Enterprise,” was hosted by the EDA Consortium and based on Dr. Bose’s career in building several businesses in the high-tech industry.
Continuing on the theme of FinFET layout, let’s consider what you have to do for routing. Again drawing on the experience of my layout colleagues who are still ‘in the business’ and dealing with FinFETs, here are a few landmines you will have to deal with.
One particular issue they encounter is that although the base layers have shrunk considerably, the shrink of the routing layers has not kept pace. Each new node has brought us smaller transistors, but the minimum metal pitch has not really changed. This really impacts layout floorplanning because designs that were once dictated by device area are now dictated by the ability to route the required signals. Double-/triple-patterning compounds the issue even further.
The two questions I hear most often while doing presentations about SCE-MI transaction based emulation are “Can we have coffee break?” and “Why do we need a thin C layer between two SystemVerilog tops”?
You a probably reading this during a coffee break, so let’s jump to second question. It refers to this diagram showing how to connect a SystemVerilog testbench (usually UVM) with DUT in SystemVerilog using a DPI transactor, as defined by the Function-based.
